 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| june 2006 rev 1 1/126 1 L9803 super smart power motor driver with 8-bit mcu, ram, eeprom, adc, wdg, timers, pwm and h-bridge driver features 6.4-18v supply operating range 16 mhz maximum oscillator frequency 8 mhz maximum internal clock frequency oscillator supervisor fully static operation -40c to + 150c temperature range user rom: 16 kbytes data ram: 256 bytes data rom: 128 bytes 64 pin hiquad64 package 10 multifunctional bi directional i/o lines two 16-bit timers, each featuring: ? 2 input captures ? 2 output compares ? external clock input (on timer 1) ? pwm and pulse generator modes two programmable 16-bit pwm generator modules. can peripheral includ ing bus line interface according 2a/b passive specifications 10-bit analog-to-digital converter software watchdog for system integrity master reset, power-on reset, low voltage reset 90m ? dmos h-bridge. 8-bit data manipulation 63 basic instructions and 17 main addressing modes 8 x 8 unsigned mult iply instruction true bit manipulation complete development support on dos/windows tm real-time emulator full software packag e on dos/windows? (c-compiler, cross-a ssembler, debugger). order codes hiquad64 part number package packing L9803 hiquad64 tray www.st.com
contents L9803 2/126 contents 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 clocks, reset, interrupts & power saving modes . . . . . . . . . . . . . . . . 18 3.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 oscillator safeguard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.1 dedicated control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 watchdog system (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.3 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.4 power-on reset - low voltage detection . . . . . . . . . . . . . . . . . . . . . . . 25 3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 L9803 contents 3/126 4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 digital section power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.1 vdd short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 analog section power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.1 vcc short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4 pwm i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.2 pwmo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.3 pwmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5 10-bit a/d converter (ad10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5.3 input selections and sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.4 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.5 temperature sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.6 precise temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.6 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 contents L9803 4/126 5.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7 can bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.7.4 can transceiver disabling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.8 power bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.8.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.8.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.8.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.9 eeprom (eep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.9.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.3 application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.5 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.6 operating block electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 120 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 L9803 list of tables 5/126 list of tables table 1. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. recommended values for 16 mhz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. watchdog timing (fosc = 16 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 6. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7. port a configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8. port b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 10. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 11. pwm timing (fcpu = 8mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 12. adc channel selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 13. can register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 14. functional description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 15. st7 addressing mode overview: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 16. absolute maximum ratings (voltage referenced to gnd) . . . . . . . . . . . . . . . . . . . . . . . 114 table 17. thermal characteristics (vb=18v, tj = 150c, iload = 2a) . . . . . . . . . . . . . . . . . . . . . 115 table 18. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 19. control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 20. a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 21. power bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 22. eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 23. pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 24. pwm input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 25. oscillator safeguard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 26. can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 27. power on/low voltage reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 28. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 list of figures L9803 6/126 list of figures figure 1. L9803 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. pin out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. organization of internal cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 4. stack manipulation on interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. external clock source connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 6. crystal/ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. clock prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. timing diagram for internal cpu clock frequency transitions . . . . . . . . . . . . . . . . . . . . . 20 figure 9. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. power up/down behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. wait mode flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. halt mode flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. voltage regulation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 18. ports pa0-pa7, pb0-pb1i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 26. output compare timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . 49 figure 27. one pulse mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 28. pulse width modulation mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 29. pwm cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 30. pwm generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 31. pwm block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 32. pwm i/o block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 33. impedance at pwmo/i pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 34. pwmi function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 35. block diagram of the analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 36. temperature sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 37. can block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 38. can frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 39. can controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 40. can error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 41. bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 42. can register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 43. page maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 44. can bus transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 figure 45. power bridge schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 46. example - power bridge waveform, pwm up brake driving mode. . . . . . . . . . . . . . . . . . 99 figure 47. eeprom block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 48. data eeprom programmin g cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 L9803 list of figures 7/126 figure 49. eeprom programming fl owchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 50. hiquad-64: qja. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 51. hiquad-64: thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 52. application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 53. hiquad-64 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 general description L9803 8/126 1 general description 1.1 introduction the L9803 is a super smart power device suited to drive resistive and inductive loads under software control. it includes a st7 microcontroller and some pheripherals. the microcontroller can execute the software contained in the program rom and drive, through dedicated registers, the power bridge. the internal voltage regulators rated to the automotive environment, pwm modules, can transceiver and controller, timers, temperature sensor and the atod converter allow the device to realize by itself a complete application, in line wit h the most common mechatronic requirements. L9803 general description 9/126 figure 1. L9803 block diagram 8-bit core alu address and data bus oscin oscout 10-bit adc watchdog osc internal clock control rom 16k port a pa0 -> pa7 osc safeguard port b pb0 -> pb1 timer 1 timer 2 pwm 2 pwm 1 pwmi pwmo pwmo ad2 ad3 ad4 ram 256b eeprom 128b v cc v dd power supply vb2 preregulator agnd gnd nreset power bridge vbr vbl pgnd outr outl can controller can transceiver can_h can_l rx tx temp sensor pwmi tm vb1 general description L9803 10/126 1.2 pin out figure 2. pin out 1.3 pin description ad2-ad4: analog input to adc. pa0/ocmp2_1-pa1/ocmp1_1: i/os or output compares on timer 1. alternate function software selectable (by setting oc2e or oc1e in cr2 register: bit 6 or 7 at 0031h). when used as an alternate function, this pin is a push-pull output as requested by timer 1. otherwise, this pin is a triggered floating input or a push-pull output. pa2/icap2_1-pa3/icap1_1: i/ os or input captures on timer 1. before using this i/o as alternate inputs, they must be configured by software in input mode (ddr=0). in this case, these pins are a triggered floating input. otherwise (i/o function), these pin are triggered floating inputs or push-pull outputs. pa4/extclk_1: pa4 i/o or external clock on timer 1 . before using this i/o as alternate input, it must be configured by software in input mode (ddr=0). in this case, this pin is a triggered floating input. otherwise (i/o function) , this pin is a triggered floating input or a push-pull output. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 nu nu nu ad3 ad2 pa1/ocmp1_1 pa0/ocmp2_1 tm vdd oscin oscout gnd nu vbl vbl vbl nu nu nu nu nu pb1/extclk_2 nu nu pwmo pwmi nreset can_h can_l gnd vdd vb2 vb1 vbr vbr vbr nu nu nu nu nu nu outl outl outl pgnd pgnd outr outr outr nu nu vcc agnd ad4 pa2/icap2_1 pa3/icap1_1 pgnd pgnd pa4/extclk_1 pa5/ocmp2_2 pa6/ocmp1_2 pa7/icap2_2 pb0/icap1_2 L9803 general description 11/126 pa5/ocmp2_2-pa6/ocmp1_2: i/os or output compares on timer 2 . alternate function software selectable (by setting oc2e or oc1e in cr2 register: bit 6 or 7 at 0041h). when used as alternate functions, these pins are push-pull outputs as requested by timer 2. otherwise, these pins are triggered floating inputs or push-pull outputs. pa7/icap2_2-pb0/icap1_2: i/os or input captures on timer 2 . before using these i/os as alternate inputs, they must be configured by software in input mode (ddr=0). in this case, these pins are triggered floating inputs. otherwise (i/o function), these pins are triggered floating inputs or push-pull outputs. pb1/extclk_2: pb1 i/o or external clock on timer 2 . before using this i/o as alternate input, it must be configured by software in input mode (ddr=0). in this case, this pin is a triggered floating input. otherwise (i/o function) , this pin is a triggered floating input or a push-pull output. tm : input. this pin must be held low during normal operating modes. vdd : output. 5v power supply for digital circuits, from internal voltage regulator. oscin: input oscillator pin. oscout : output oscillator pin. gnd: ground for digital circuits. vbr: power supply for right half-bridge. outr: output of left half-bridge. pgnd: ground for power transistor. outl: output of right half-bridge. vbl: power supply for left half-bridge. vb1 : power supply for voltage regulators. vb2 : pre-regulated voltage for analog circuits. can_l: low side can bus output. can_h: high side can bus input. nreset: bidirectional. this active low signal forces the initialization of the mcu. this event is the top priority non maskable interrupt. it can be used to reset external peripherals. pwmi: pwm input. directly connected to input capture 2 on timer 2. pwmo: pwm output. connected to the output of pwm2 module. agnd: ground for all analog circuitry (except power bridge) . vcc: output. 5v power supply for analog circuits, from internal voltage regulator. 1.4 register & memory map as shown in the ta bl e 1 , the mcu is capable of addressing 64k bytes of memories and i/o registers. in this mcu, 63742 of these bytes are user accessible. the available memory locations consist of 128 bytes of i/o registers, 256 bytes of ram, 128 bytes of eeprom and 16kbytes of user rom. the ram space includes 64bytes for the stack from 0140h to 017fh. general description L9803 12/126 the highest address bytes contain the user reset and interrupt vectors. table 1. memory map address block register label register name reset status remarks 0000h 0001h 0002h 0003h port a padr .. paddr .. paor .. data register data direction register option register not used 00h 00h 00h r/w r/w r/w absent 0004h 0005h 0006h 0007h port b pbdr .. pbddr .. pbor .. data register data direction register option register not used 00h 00h 00h r/w r/w r/w absent 0008h to 000fh reserved 0010h 0011h 0012h 0013h 0014h 0015h 0016h pwm1 p1cyrh .. p1cyrl .. p1drh .. p1drl .. p1cr .. p1cth .. p1ctl .. pwm1 cycle register high pwm1 cycle register low pwm1 duty register high pwm1 duty register low pwm1 control register pwm1 counter register high pwm1 counter register low 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w read only read only 0017h reserved 0018h 0019h 001ah 001bh 001ch 001dh 001eh pwm2 p2cyrh .. p2cyrl .. p2drh .. p2drl .. p2cr .. p2cth .. p2ctl .. pwm2 cycle register high pwm2 cycle register low pwm2 duty register high pwm2 duty register low pwm2 control register pwm2 counter register high pwm2 counter register low 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w read only read only 001fh reserved 0020h miscr .. miscellaneous register 00h see section 3.4 0021h power bridge pbcsr .. bridge control status register 00h r/w 0022h dcsr .. dedicated control status register 00h r/w 0023h to 0029h reserved 002ah 002bh wdg wdgcr .. wdgsr .. watchdog control register watchdog status register 7fh 00h r/w r/w 002ch eeprom eecr .. eeprom control register 00h r/w 002dh 002eh reserved 002fh 0030h reserved L9803 general description 13/126 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h 003ah-003bh 003ch-003dh 003eh-003fh tim1 t1cr2 .. t1cr1 .. t1sr .. t1ic1hr .. t1ic1lr .. t1oc1hr .. t1oc1lr .. t1chr .. t1clr .. t1achr .. t1aclr .. t1ic2hr .. t1ic2lr .. t1oc2hr .. t1oc2lr .. timer 1 control register2 timer 1 control register1 timer 1 status register timer 1 input capture1 high register timer 1 input capture1 low register timer 1 output compare1 high register timer 1 output compare1 low register timer 1 counter high register timer 1 counter low register timer 1 alternate counter high register timer 1 alternate counter low register timer 1 input capture2 high register timer 1 input capture2 low register timer 1 output compare2 high register timer 1 output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch ffh fch xxh xxh xxh xxh r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved: write forbidden 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004ah-004bh 004ch-004dh 004eh-004fh tim2 t2cr2 .. t2cr1 .. t2sr .. t2ic1hr .. t2ic1lr .. t2oc1hr .. t2oc1lr .. t2chr .. t2clr .. t2achr .. t2aclr .. t2ic2hr .. t2ic2lr .. t2oc2hr .. t2oc2lr .. timer 2 control register2 timer 2 control register1 timer 2 status register timer 2 input capture1 high register timer 2 input capture1 low register timer 2 output compare1 high register timer 2 output compare1 low register timer 2 counter high register timer 2 counter low register timer 2 alternate counter high register timer 2 alternate counter low register timer 2 input capture2 high register timer 2 input capture2 low register timer 2 output compare2 high register timer 2 output compare2 low register 00h 00h xxh xxh xxh xxh xxh ffh fch 00h 00h xxh xxh xxh xxh r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h to 0059h reserved 005ah 005bh 005ch 005dh 005eh 005fh 0060h to 006fh can canisr .. canicr .. cancsr .. canbrpr .. canbtr .. canpsr .. can interrupt status register can interrupt control register can control/status register can baud rate prescaler can bit timing register can page selection can first address to last address of page x 00h 00h 00h 00h 23h 00h -- r/w r/w r/w r/w r/w r/w see page mapping and register description 0070h 0071h 0072h adc adcdrh .. adcdrl .. adccsr .. adc data register high adc data register low adc control/status register 00h 00h 20h read only read only r/w table 1. memory map (continued) address block register label register name reset status remarks general description L9803 14/126 address block description 0080h to 013fh ram 256 bytes including stack 64 bytes (0140h to 017fh) user variables and subroutine nesting 0140h to 017fh 0180h to 0bffh reserved 0c00h to 0c7fh eeprom 128 bytes including 4 bytes reserved for temperature sensor trimming (see section 5.5.6 ) 0c7ch: t0h 0c7dh: t0l 0c7eh: vt0h 0c7fh: vt0l 0c80h to bfffh reserved c000 to ffdfh rom 16k bytes (16384 bytes) user application code and data ffe0h to ffffh interrupt and reset vectors L9803 central processing unit 15/126 2 central processing unit 2.1 introduction the cpu has a full 8-bit architecture. six internal registers allow efficient 8-bit data manipulation. the cpu is capable of executing 63 basic instructions and features 17 main addressing modes. 2.2 cpu registers the 6 cpu registers are shown in the programming model in figure 3 . following an interrupt, all registers except y are pushed onto the stack in the order shown in figure 4 . they are popped from stack in the reverse order. the y register is not affected by these automatic procedures. the interrupt routine must therefore handle y, if needed, through the push and pop instructions. accumulator (a). the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. index registers (x and y). these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register. program counter (pc). the program counter is a 16-bit regi ster containing the address of the next instruction to be executed by the cpu. figure 3. organization of internal cpu registers accumulator: x index register: y index register: stack pointer: condition code register: program counter: x = undefined 15 reset value: 70 xx xxxxxx reset value: 70 1x 1 1 x1 xx 1c 11hi nz reset value = reset vector @ fffeh-ffffh reset value: 70 xx xxxxxx reset value: 70 xx xxxxxx 70 15 70 01 000000 reset value =0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 central processing unit L9803 16/126 stack pointer (sp) the stack pointer is a 16-bit register. since the stack is 64 bytes deep, the most significant bits are forced as indicated in figure 3 in order to address the stack as it is mapped in memory. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer is set to point to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the upper and lower limits of the stack area are shown in the memory map. the stack is used to save the cpu context during subroutine calls or interrupts. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt (refer to figure 4 ), the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations. when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. condition code register (cc) the condition code register is a 5-bit register which indicates the result of the instruction just executed as well as the state of the processor. these bits can be individually tested by a program and specified action taken as a result of their state. the following paragraphs describe each bit of the cc register in turn. half carry bit (h) the h bit is set to 1 when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. the h bit is useful in bcd arithmetic subroutines. interrupt mask (i) when the i bit is set to 1, all interrupts except the trap software interrupt are disabled. clearing this bit enables interrupts to be passed to the processor core. interrupts requested while i is set are latched and can be processed when i is cleared (only one interrupt request per interrupt enable flag can be latched). negative (n) when set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is negative (i.e. the most significant bit is a logic 1). zero (z) when set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. carry/borrow (c) when set, c indicates that a carry or borrow out of the alu occured during the last arithmetic operation. this bit is also affected during execution of bit test, branch, shift, rotate and store instructions. L9803 central processing unit 17/126 figure 4. stack manipulation on interrupt condition code accumulator x index register pch pcl 111 0 7 higher address lower address context restored context saved on interrupt on return clocks, reset, interrupts & power saving modes L9803 18/126 3 clocks, reset, interrupts & power saving modes 3.1 clock system 3.1.1 general description the mcu accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. the internal clock (f cpu ) is derived from the external oscillator frequency (f osc ) . the external oscillator clock is first divi ded by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in slow mode, to reduce the frequency of the f cpu ; this clock signal is also routed to the on-c hip peripherals (except the can). the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz crystal resonator in the frequency range specified for f osc . the circuit shown in figure 6 is recommended when using a crystal, and ta b l e 2 lists the recommended capacitance and feedback resistance values. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. use of an external cmos oscillator is reco mmended when crystals outside the specified frequency ranges are to be used. table 2. recommended values for 16 mhz crystal resonator note: r smax is the equivalent serial resistor of the crystal (see crystal specification). c oscin ,c oscout : maximum total capacitances on pins oscin and oscout (the value includes the external capacitance tied to the pi n plus the parasitic c apacitance of the board and of the device). rp: external shunt resistance. recommend ed value for oscillator stability is 1m ? . figure 5. external clock source connections r smax 40 ? 60 ? 150 ? c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m ? 1-10 m ? 1-10 m ? osc in osc out external clock nc L9803 clocks, reset, interrupts & power saving modes 19/126 figure 6. crystal/ceramic resonator figure 7. clock prescaler block diagram 3.1.2 external clock an external clock may be applied to the oscin input with the oscout pin not connected, as shown on figure 5 . the t oxov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov . osc in osc out c oscin c oscout r p osc in osc out c oscin c oscout r p %2 %2,4,8,16 cpuclk to cpu and peripherals to can clocks, reset, interrupts & power saving modes L9803 20/126 figure 8. timing diagram for internal cpu clock frequency transitions 3.2 oscillator safeguard the L9803 contains an oscillator safe guard function. this function provides a real time check of the crystal os cillator generating a reset condition when the clock frequency has anomalous value. if f osc L9803 clocks, reset, interrupts & power saving modes 21/126 this flag is useful for distinguishing safeguard reset, power on / low voltage reset and watchdog reset. b7 = sgfl: safeguard low flag. set by an osc illator safeguard reset generated for frequency too low, cleared by software (writing zero) or power on / low voltage reset. this flag is useful for distinguishing safeguard reset, power on / low voltage reset and watchdog reset. b5 = sfgen : safeguard enable when set. it?s cleared only by hardware after a reset. b4 = cands : can transceiver disable. when this bi t is set the can transceiver goes in power down mode and does not work until this bit is reset. cands is 0 after reset so the standard condition is with the transceiver enabled. this bit can be used by application requiring low power consumption (see section 5.8 for details). b3,b2,b1 = not used b0 = pien : pwmi input enable. when set, the pwmi input line is connected to input capture 2 of timer 2. otherwise, icap2_2 is the alternate function of pa7. see figure 34 for the explanation of this function. 3.3 watchdog system (wdg) 3.3.1 introduction the watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logi cal conditions, which causes the application program to give up its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before it is decremented to zero. 3.3.2 main features ? programmable timer (64 increments of 12,288 cpu clock) ? programmable reset ? reset (if watchdog activated) after an halt instruction or when bit timer msb reaches zero ? watchdog reset indicated by status flag. 3.3.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 become s cleared), it initiates a rese t cycle pulling low the reset pin for typically 500ns. clocks, reset, interrupts & power saving modes L9803 22/126 the application program must write in the cr register at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 1): ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an immediate reset ? the t5:t0 bit contain the number of in crements which represents the time delay before the watchdog produces a reset. note: following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. figure 9. functional description the watchdog delay time is defined by bits 5-0 of the watchdog register; bit 6 must always be set in order to avoid generating an immediate reset. conversely, this can be used to generate a software reset (bit 7 = 1, bit 6 = 0). the watchdog must be reloaded before bit 6 is decremented to ?0? to avoid a reset. following a reset, the watchdog regi ster will contain 7fh (bits 0-7). if the circuit is not used as a watchdog (i.e. bi t 7 is never set), bits 6 to 0 may be used as a simple 7-bit timer, for instance as a real ti me clock. since no reset will be generated under these conditions, the watchdog control register must be monitored by software. table 3. watchdog timing (f osc = 16 mhz) wdg register initial value wdg timeout period (ms) ffh 98.3 c0h 1.54 reset wdga 7-bit downcounter f cpu msb lsb clock divider wdgf watchdog status register (wdgsr) watchdog control register (wdgcr) 12288 L9803 clocks, reset, interrupts & power saving modes 23/126 a flag in the watchdog status register indicates if the last reset is a watchdog reset or not, before clearing by a write of this register. 3.3.4 register description watchdog control register (wdgcr) register address: 002ah ? read/write reset value: 0111 1111 (7fh) b7 = wdga: activation bit. this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled. b6-0 = t6-t0 : 7 bit timer (msb to lsb) these bits contain the decremented value. a rese t is produced when it rolls over from 40h to 3fh (t6 become cleared). watchdog status register (wdgsr) register address: 002bh ? read/write reset value (*) : 0000 0000 (00h) b7-1 = not used b0 = wdgf: watchdog flag. set by a watchdog reset, cleared by software (writing zero) or power on / low voltage reset. this flag is us eful for distinguishing power on / low voltage reset and watchdog reset. (*): except in the case of watchdog reset. 3.4 miscellaneous register (miscr) the miscellaneous register allows the user to select the slow operating mode and to set the clock division prescaler factor. bits 3, 4 determ ine the signal conditions which will trigger an interrupt request on i/o pins having interrupt capability. register address: 0020h ? read/write 7 0 wdga t6 t5 t4 t3 t2 t1 t0 7 0 -- ---- - wdgf clocks, reset, interrupts & power saving modes L9803 24/126 reset value:0000 0000 (00h) b0 - slow mode select 0- normal mode - oscillator frequency / 2 (reset state) 1- slow mode (bits b1 and b2 define the prescaler factor) b1, b2 - cpu clock prescaler for slow mode b3, b4 - external interrupt option the selection issued from b3/b4 combination is applied to pa[0]..pa[7],pb0,pb1 external interrupt. the selection can be made only if i bit in cc register is reset (interrupt enabled). b3, b4 can be written only when the interrupt mask (i) of the cc (condition code) register is set to 1. b5,b6,b7 = not used 3.5 reset 3.5.1 introduction there are four sources of reset: ? nreset pin (external source) ? power-on reset / low voltage detection (internal source) ? watchdog (internal source) ? safeguard (internal source) the reset service routine vector is located at address fffeh-ffffh. - - - b4b3 b2 b1b0 b2 b1 option 0 0 oscillator frequency / 4 1 0 oscillator frequency / 8 0 1 oscillator frequency / 16 1 1 oscillator frequency / 32 b4 b3 option 0 0 falling edge and low level (reset state) 1 0 falling edge only 0 1 rising edge only 1 1 rising and falling edge L9803 clocks, reset, interrupts & power saving modes 25/126 3.5.2 external reset the nreset pin is both an input and an open- drain output with integrated pull-up resistor. when one of the internal reset sources is active, the reset pin is driven low to reset the whole application. 3.5.3 reset operation the duration of the reset condition, which is also reflected on the output pin, is fixed at 4096 internal cpu clock cycles. a reset signal originating from an external source must have a duration of at least 1.5 internal cpu clock cycles in order to be recognised. at the end of the power-on reset cycle, the mcu may be held in the reset condition by an external reset signal. the nreset pin may thus be used to ensure v dd has risen to a point where the mcu can operate correctly before the user program is run. following a power-on reset event, or after exiting halt mode, a 4096 cpu clock cycle delay period is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the reset state. during the reset cycle, the device reset pin acts as an output that is pulsed low. in its high state, an internal pull-up resistor of about 300k ? is connected to the reset pin. this resistor can be pulled low by external circuitry to reset the device. 3.5.4 power-on reset - low voltage detection the por/lvd function generates a static reset when the supply voltage is below a reference value. in this way, the power-on reset and low voltage reset function are provided, in order to keep the system in safe condition when the voltage is too low. the power-up and power-down thresholds are different, in order to avoid spurious reset when the mcu starts running and sinks current from the supply. the lvd reset circuitry generates a reset when v dd is below: ?v reseton when v dd is rising ?v resetoff when v dd is falling the por/lvd function is explained in figure 11 . power-on reset activates the reset pull up transistor performing a complete chip reset. in the same way a reset can be triggered by the watchdog, by the safeguard or by external low level at nreset pin. an external capacitor connected between nreset and ground can extend the power on reset period if required. clocks, reset, interrupts & power saving modes L9803 26/126 figure 10. power up/down behaviour figure 11. reset block diagram = undefined value 5v t v reset ud v reset off v reset on 5v t v dd por/lvd internal reset oscillator signal counter nreset to st7 reset v dd watchdog reset safeguard reset por/lvd reset 300k reset clk L9803 clocks, reset, interrupts & power saving modes 27/126 3.6 interrupts a list of interrupt sources is given in ta bl e 4 below, together with relevant details for each source. interrupts are serviced according to their order of priority, starting with i0, which has the highest priority, and so to i12, which has the lowest priority. the following list describes the or igins for each interrupt level: ? i0 connected to ports pa0-pa7, pb0-pb1 ? i1 connected to can ? i2 connected to power diagnostics ? i3 connected to output compare of timer 1 ? i4 connected to input capture of timer 1 ? i5 connected to timer 1 overflow ? i6 connected to output compare of timer 2 ? i7 connected to input capture of timer 2 ? i8 connected to timer 2 overflow ? i9 connected to adc end of conversion ? i10 connected to pwm 1 overflow ? i11 connected to pwm 2 overflow ? i12 connected to eeprom exit from halt mode may only be triggered by an external interrupt on one of the following ports: pa0-pa7 (i0), pb0-pb1 (i0), or by an internal interrupt coming from can peripheral (i1). if more than one input pin of a group connected to the same interrupt line are selected simultaneously, the or of this signals generates the interrupt. table 4. interrupt mapping interrupts register flag name interrupt source vector address reset n/a n/a - fffeh-ffffh software n/a n/a - fffch-fffdh ext. interrupt (ports pa0-pa7, pb0- pb1) n/a n/a i0 fffah-fffbh receive interrupt flag can status rxifi i1 fff8h-fff9h transmit interrupt flag txif error interrupt pending epnd power bridge short circuit bridge control status sc i2 fff6h-fff7h overtemperature ovt output compare 1 timer 1 status ocf1_1 i3 fff4h-fff5h output compare 2 ocf2_1 input capture 1 timer 1 status icf1_1 i4 fff2h-fff3h input capture 2 icf2_1 clocks, reset, interrupts & power saving modes L9803 28/126 figure 12. interrupt processing flowchart note: 1 see ta bl e 4 timer overflow timer 1 status tof_1 i5 fff0h-fff1h output compare 1 timer 2 status ocf1_2 i6 ffeeh-ffefh output compare 2 ocf2_2 input capture 1 timer 2 status icf1_2 i7 ffech-ffedh input capture 2 icf2_2 timer overflow timer 2 status tof_2 i8 ffeah-ffebh adc end of conversion adc control eoc i9 ffe8h-ffe9h pwm 1 overflow n/a n/a i10 ffe6h-ffe7h pwm 2 overflow n/a n/a i11 ffe4h-ffe5h eeprom programming eeprom c ontrol e2ite i12 ffe2h-ffe3h table 4. interrupt mapping (continued) interrupts register flag name interrupt source vector address interrupt trap i bit = 1 y y n set i bit to 1 push pc,x,a,cc onto stack load pc wuth appropriate interrupt vector (1) execute instruction fetch next instruction of appropriate interrupt service routine L9803 clocks, reset, interrupts & power saving modes 29/126 3.7 power saving modes 3.7.1 introduction there are three power saving modes. the slow mode may be selected by setting the relevant bits in the miscellaneous register as detailed in section 3.4 . wait and halt modes may be entered using the wfi and halt instructions. 3.7.2 slow mode in slow mode, the oscillator frequen cy can be divided by 4, 8, 16 or 32 rather than by 2. the cpu and peripherals (except can, see note) are clocked at this lower frequency. slow mode is used to reduce power consumption. note: before entering slow mode and to guarantee low power operations, the can controller must be placed by software in standby mode. 3.7.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. all peripherals remain active. during wait mode, the i bit (cc register) is cleared, so as to enable all interrupts. all other register s and memory remain unchanged. the mcu will remain in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt (coming from can, timers 1 & 2, eeprom, adc, pwm 1 & 2, i/o ports peripherals and power bridge) occurs, causing its wake-up. refer to figure 12 below. figure 13. wait mode flow chart wait instruction reset fetch reset vector or service interrupt interrupt y n n y cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit on on cleared off clocks, reset, interrupts & power saving modes L9803 30/126 3.7.4 halt mode the halt mode is the mcu lowest power consumption mode. the halt mode is entered by executing the halt instruction. the internal osc illator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the cc register is cleared so as to enable external interrupts. if an interrupt occurs, the cpu becomes active. the mcu can exit the halt mode upon reception of either an external interrupt (i0), a internal interrupt coming from the can peripheral (i1) or a reset. the oscillator is then turned on and a stabilisation time is provided before re leasing cpu operation. the stabilisation time is 4096 cpu clock cycles. after the start up delay, the cpu continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. note: the halt mode cannot be used when the watchdog or the safeguard are enabled, if the halt instruction is executed while the watchdog or safeguard system are enabled, a reset is automatically generated thus resetting the entire mcu. halt mode affects only the digital section of the device. all the analog circuit remain in their status, including adc, voltage regulators, bus transceivers and power bridge. figure 14. halt mode flow chart n n external interrupt reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y L9803 voltage regulator 31/126 4 voltage regulator 4.1 introduction the on chip voltage regulator provides two regulated voltage, nominally 5v both. vcc supplies adc and the analog periphery and vdd supplies the microcontroller and logic parts. these voltage are available at pins vdd and vcc to supply external components and connects a capacitors to optimize emi performance. a pre-regulator circuit allows to connect external tantalum capacitors to a lower (10v) voltage (vb2 pin). 4.1.1 functional description the main supply voltage is taken from vb1 pin. a voltage pre-regulator provides the regulated voltage on pin vb2. vb2 is the supply for the digital and analog regulators. the block diagram shows the connections between the regulators and the external pins. in order to prevent negative spikes on the battery line to propagate on the internal supply generating spurious reset, a series diode supply vb1 pin is recommended. figure 15. voltage regulation block diagram adc pre-regulator vb1 vb2 force analog voltage regulator sense vcc agnd digital voltage regulator vdd gnd battery voltage regulator L9803 32/126 4.2 digital section power supply the digital supply voltage vdd is available at pin number 42 and 9. the digital ground gnd is available at pin number 43 and 12. pin 42 and 43 are the actual voltage regulator output and external loads must be supply by these pin. the 100nf compensation capacitor should be connected as close as possible to pin 42 and 43. pin number 9 and 12 provide an external access to the internal oscillator supply. resonator?s capacitors should be grounded on pin 12. the application board can improve noise reduction in the chip connecting directly pin 42 to pin 9 and pin 43 to pin 12 using traces as s hort as possible. an additional capacitor mounted close to pin 9 and 12 can lead additional improvement. 4.2.1 vdd short ci rcuit protection the output current of the digital voltage regulator is controlled by a circuit that limits it to a maximum value (i maxvdd ). when the output current exceeds this value the vdd voltage starts falling down. external loads must be ch osen taking in account this maximum current capability of the regulator. 4.3 analog section power supply the analog supply voltage is available on vcc pin. the external 100nf compensation capacitor should be placed as close as possible to this pin and agnd pin. vcc is the reference voltage for the ad conversion and must be used to supply ratiometric sensors feeding ad inputs. any voltage drop between vcc pin and the sensor supply pin on the application board, will cause the adc to be inaccurate when reading the sensor?s output. 4.3.1 vcc short ci rcuit protection the output current of the analog voltage regulator is controlled by a circuit that limits it to a maximum value (i maxvcc ). when the output current exceeds this value the vcc voltage starts falling down. external loads must be ch osen taking in account this maximum current capability of the regulator. warning: the pin vb2 is not short circuit protected so a short circuit on this pin will destroy the device. L9803 on-chip peripherals 33/126 5 on-chip peripherals 5.1 i/o ports 5.1.1 introduction the internal i/o ports allow the transfer of data through digital inputs and outputs, the interrupt generation coming from an i/o and for specific pins, the input/output of alternate signals for the on-chip peripherals (timers...). each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.1.2 functional description each port has 2 main registers: ? data register (dr) ? data direction register (ddr) and one optional register: ? option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not provide this register refer to the i/o port implementation section). the generic i/o block diagram is shown in figure 16 . input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 1. writing the dr register modifies the latch value but does not affect the pin status. 2 2. when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 3. do not use r ead/modify/write instructions (bset or bres) to modify the dr register external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the miscellaneous register. each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several input pins are selected simultaneously as interrupt source, these are logically nanded. for this reason if one of the interrupt pins is tied low, it masks the other ones. on-chip peripherals L9803 34/126 in case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see figure 17 ). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellaneous register must be modified. output mode the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digi tally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. dr push-pull open-drain 0 vss vss 1 v dd floating L9803 on-chip peripherals 35/126 figure 16. i/o port general block diagram legend: ni - not implemented off - implemented not activated on - implemented and activated note: the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the device against positive stress. table 5. i/o port mode options configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up configuration p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access on-chip peripherals L9803 36/126 table 6. i/o port configurations note: 1 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate fu nction output status. 2 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function re ads the pin status given by the dr register content. caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port.switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommended safe transitions are illustrated in figure 17 . other transitions are potentially risky and should hardware configuration input 1) open-drain output 2) push-pull output 2) configuration pad v dd r pu external interrupt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register configuration alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports L9803 on-chip peripherals 37/126 be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 17. interrupt i/o port state transitions i/o port implementation the i/o port register configurations are resumed as following. port pa(7:0), port pb(2:0) reset status: dr=0, ddr=0 and or=0 (input mode, no interrupt). these ports offer interrupt capabilities. ddr or mode 00 input no interrupt (pull-up enabled) 01 input interrupt (pull-up enabled) 1 0 open-drain output 1 1 push-pull output 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or on-chip peripherals L9803 38/126 dedicated configurations . table 7. port a configuration port a i / o function input output alternate interrupt pa0 triggered with pull-up push-pull/open drain ocmp2_1: output compare #2 timer 1 wake-up interrupt (i0) pa1 triggered with pull-up push-pull/open drain ocmp1_1: output compare #1 timer 1 wake-up interrupt (i0) pa2 triggered with pull-up push-pull/open drain icap2_1: input capture #2 timer 1 wake-up interrupt (i0) pa3 triggered with pull-up push-pull/open drain icap1_1: input capture #1 timer 1 wake-up interrupt (i0) pa4 triggered with pull-up push-pull/open drain extclk_1: external clock timer 1 wake-up interrupt (i0) pa5 triggered with pull-up push-pull/open drain ocmp2_2: output compare #2 timer 2 wake-up interrupt (i0) pa6 triggered with pull-up push-pull/open drain ocmp1_2: output compare #1 timer 2 wake-up interrupt (i0) pa7 triggered with pull-up push-pull/open drain icap2_2: input capture #2 timer 2 wake-up interrupt (i0) table 8. port b configuration port b i / o function input output alternate interrupt pb0 triggered with pull-up push-pull/open drain icap1_2: input capture #1 timer 2 wake-up interrupt (i0) pb1 triggered with pull-up push-pull/open drain extclk_2: external clock timer 2 wake-up interrupt (i0) pb2 (1) not connected to pad not connected to pad pwmi: pwm input 1. the pb2 bit is not connected to the external. it must be configured as an input without interrupt, to be used only as an alternate function. L9803 on-chip peripherals 39/126 figure 18. ports pa0-pa7, pb0-pb1i dr ddr latch latch data bus dr sel ddr sel vdd pad m u x alternate alternate digital enable alternate enable alternate m u x alternate input output p-buffer n-buffer 1 0 1 0 or latch or sel from other bits interrupt pull-up condition enable enable gnd on-chip peripherals L9803 40/126 5.1.3 register description data registers (padr) port a: 0000h read/write reset value: 0000 0000 (00h) (pbdr) port b: 0004h read/write reset value: 0000 0000 (00h) data direction registers (paddr) port a: 0001h read/write reset value: 0000 0000 (00h) (input mode) (pbddr) port b: 0005h read/write reset value: 0000 0000 (00h) (input mode) 7 0 msb lsb 7 0 msb 0 0 0 0 lsb 7 0 msb lsb 7 0 msb 0 0 0 0 lsb L9803 on-chip peripherals 41/126 option registers (paor) port a: 0002h read/write reset value: 0000 0000 (00h) (no interrupt) (pbor) port b: 0006h read/write reset value: 0000 0000 (00h) (no interrupt) 5.2 16-bit timer 5.2.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. 7 0 msb lsb 7 0 msb 0 0 0 0 lsb on-chip peripherals L9803 42/126 5.2.2 main features programmable prescaler: f cpu divided by 2, 4 or 8. overflow status flag and maskable interrupt external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge output compare functions with ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt input capture functions with ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode 5 alternate functions on i/o ports the block diagram is shown in figure 19 on page 43 . note: some external pins are not available on all devices. refer to the device pin out description. 5.2.3 functional description counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter regi ster (cr): ? counter high register (chr) is th e most significant byte (ms byte). ? counter low register (clr) is the least significant byte (ls byte). alternate counter register (acr) ? alternate counter high register (achr) is the most significant byte (ms byte). ? alternate counter low regi ster (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counters is also fffch in one pulse mode and pwm mode. L9803 on-chip peripherals 43/126 the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in table 9: clock control bits . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles depe nding on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. figure 19. timer block diagram mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 exclk cpu clock timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc1 cc0 16 bit free running counter on-chip peripherals L9803 44/126 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the lsb of the count value at the time of the read. an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1register is set and ? i bit of the ccr register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done by: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). external clock the external clock (where available) is sele cted if cc0=1 and cc1 =1 in cr2 register. the status of the exedg bi t determines the type of level tran sition on the external clock pin exclk that will trigger th e free running counter. the counter is synchronised with the falling edge of the internal cpu clock. at least four falling edges of the cpu clock must occur between tw o consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + ? t other instructions beginning of the sequence sequence completed L9803 on-chip peripherals 45/126 figure 20. counter timing diagram, internal clock divided by 2 figure 21. counter timing diagram, internal clock divided by 4 figure 22. counter timing diagram, internal clock divided by 8 input capture in this section, the index, i , may be 1 or 2 the two input capture 16-bit registers (icr1 and icr2) are used to latch the value of the free running counter after a transition detected by the icap i pin (see figure 5) . icr i register is a read-only register. ms byte ls byte icr i ichr i iclr i cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 cpu clock internal reset timer clock counter register overflow flag tof cpu clock internal reset timer clock counter register overflow flag tof fffc fffd 0000 on-chip peripherals L9803 46/126 the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( f cpu/(cc1.cc0) ). procedure to use the input capture function select the following in the cr2 register: ? select the timer clock (cc1-cc0) (see table 9: clock control bits ). ? select the edge of the active transition on the icap2 pin with the iedg2 bit. and select the following in the cr1 register: ? set the icie bit to generate an interrupt after an input capture. ? select the edge of the active transition on the icap1 pin with the iedg1 bit. when an input capture occurs: ?icf i bit is set. ?the icr i register contains the value of th e free running counter on the active transition on the icap i pin (see figure 23 ). ? a timer interrupt is generated if the icie bit is set and the i bit is cleared in the ccr register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request is done by: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the iclr i register. note: after reading the ichri register, transfer of input capture data is inhibited until the iclri register is also read. the icr i register always contains the free runn ing counter value which corresponds to the most recent input capture. during halt mode, if at least one valid input capture edge occurs on the icap i pin, the input capture detection circuitry is armed. this does not set any timer flags, and does not ?wake-up? the mcu. if the mcu is awoken by an interrupt, the input capture flag will become active, and data corresponding to the first valid edge during halt mode will be present. L9803 on-chip peripherals 47/126 figure 23. input capture block diagram figure 24. input capture timing diagram output compare in this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: ? assigns pins with a programmable value if the ocie bit is set ? sets a flag in the status register ? generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit icr1 icr2 edge detect circuit1 ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. on-chip peripherals L9803 48/126 . these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/cc[1:0] ). procedure to use the output compare function, select the following in the cr2 register: ? set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i function. ? select the timer clock (cc[1:0]) (see table 9: clock control bits ). and select the following in the cr1 register: ? select the olvl i bit to applied to the ocmp i pins after the match occurs. ? set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ?ocf i bit is set. ?the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). ? a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the ocr i register value required for a specific ti ming application can be calculated using the following formula: where: ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see table 9: clock control bits ) if the timer clock is an external clock, the formula is: ? oc i r = ? t f ext where: ? t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e.clearing the ocfi bit) is done by: 1. reading the sr register while the ocfi bit is set. 2. an access (read or write) to the ocilr register. ms byte ls byte oc i roc i hr oc i lr ? oc i r ? tf cpu ? presc ----------------------- = L9803 on-chip peripherals 49/126 the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: ? write to the oc i hr register (further compares are inhibited). ? read the sr register (first step of the clearance of the ocf i bit, which may be already set). ? write to the oc i lr register (enables the output compare function and clears the ocf i bit). figure 25. output compare block diagram figure 26. output compare timing diagram, internal clock divided by 2 forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 internal cpu clock timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) cpu writes ffff ffff fffd fffd fffe ffff 0000 fffc on-chip peripherals L9803 50/126 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (see the formula in the section). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 9: clock control bits ). . then, on a valid event on the icap1 pin, the counter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icfi bit) is done in two steps: 1. reading the sr register while the icfi bit is set. 2. an access (read or write) to the icilr register. the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: event occurs counter is reset to fffch counter = ocr1 ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 icf1 bit is set oc i r value tf cpu ? presc --------------------- -5 ? = L9803 on-chip peripherals 51/126 t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits, see table 9: clock control bits ). if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 27). note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedicated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedicated to one pulse mode. note: the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 27. one pulse mode timing pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, ocr1=2ed0h, olvl1=0, olvl2=1 on-chip peripherals L9803 52/126 the pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the formula in the section. 2. load the oc1r register with the value corresponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the section. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 9: clock control bits ). if olvl1=1 and olvl2=0, the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the ocr i register value required for a specific timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see table 9: clock control bits if the timer clock is an external clock the formula is: oc i r = t f ext -5 where: counter counter is reset to fffch ocmp1 = olvl2 counter = ocr2 ocmp1 = olvl1 when when = ocr1 pulse width modulation cycle icf1 bit is set oc i r value tf cpu ? presc --------------------- - 5 ? = L9803 on-chip peripherals 53/126 t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 28 on page 53 ). note: 1 after a write instruction to the ocihr register, the output co mpare function is inhibited until the ocilr register is also written. 2 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 28. pulse width modulation mode timing 5.2.4 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. control register 1 (cr1) timer1 register address: 0032h timer2 register address: 0042h read/write reset value: 0000 0000(00h) counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: ocr1=2ed0h, ocr2=34e2, olvl1=0, olvl2= 1 7 0 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 on-chip peripherals L9803 54/126 bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bits of the sr register are set bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bits of the sr register are set bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. 0: no effect. 1: forces the olvl2 bit to be copied to the ocmp2 pin. bit 3 = folv1 forced output compare 1. 0: no effect. 1: forces olvl1 to be copied to the ocmp1 pin. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the ocr2 register. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level tran sition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the ocr1 register. control register 2 (cr2) timer1 register address: 0031h timer2 register address: 0041h L9803 on-chip peripherals 55/126 read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 enable. 0: output compare 1 function is enabled, but the ocmp1 pin is a general i/o. 1: output compare 1 function is enabled, the ocmp1 pin is dedicated to the output compare 1 capability of the timer. bit 6 = oc2e output compare 2 enable. 0: output compare 2 function is enabled, but the ocmp2 pin is a general i/o. 1: output compare 2 function is enabled, the ocmp2 pin is dedicated to the output compare 2 capability of the timer. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the ocr1 register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of ocr1 register; the period depends on the value of ocr2 register. bit 3, 2 = cc1-cc0 clock control. the value of the timer clock depends on these bits: 7 0 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg table 9. clock control bits cc1 cc0 timer clock 00 f cpu / 4 01 f cpu / 2 10 f cpu / 8 1 1 external clock where available on-chip peripherals L9803 56/126 bit 1 = iedg2 input edge 2. this bit determines which type of level tran sition on the icap2 pin will trigger the capture 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level tran sition on the external clock pin exclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. status register (sr) timer1 register address: 0033h timer2 register address: 0043h read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value) 1: an input capture has occurred. to clear this bit, first read the sr register, then read or write the low byte of the icr1 (iclr1) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value) 1: the content of the free running counter has matched the content of the ocr1 register. to clear this bit, first read the sr register, then read or write the low byte of the ocr1 (oclr1) register. bit 5 = tof timer overflow. 0: no timer overflow (reset value) 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register do not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value) 7 0 icf1 ocf1 tof icf2 ocf2 L9803 on-chip peripherals 57/126 1: an input capture has occurred.to clear this bit, first read the sr register, then read or write the low byte of the icr2 (iclr2) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value) 1: the content of the free running counter has matched the content of the ocr2 register. to clear this bit, first read the sr register, then read or write the low byte of the ocr2 (oclr2) register. bit 2-0 = unused. input capture 1 high register (ichr1) timer1 register address: 0034h timer2 register address: 0044h read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (iclr1) timer1 register address: 0035h timer2 register address: 0045h read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 0 msb lsb 7 0 msb lsb on-chip peripherals L9803 58/126 output compare 1 high register (ochr1) timer1 register address: 0036h timer2 register address: 0046h read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oclr1) timer1 register address: 0037h timer2 register address: 0047h read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (ochr2) timer1 register address: 003eh timer2 register address: 004eh read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. . output compare 2 low register (oclr2) timer1 register address: 003fh timer2 register address: 004fh read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. . 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb L9803 on-chip peripherals 59/126 counter high register (chr) timer1 register address: 0038h timer2 register address: 0048h read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) timer1 register address: 0039h timer2 register address: 0049h read/write reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit.16-bit. alternate counter high register (achr) timer1 register address: 003ah timer2 register address: 004ah read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. . alternate counter low register (aclr) timer1 register address: 003bh timer2 register address: 004bh read/write reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb on-chip peripherals L9803 60/126 input capture 2 high register (ichr2) timer1 register address: 003ch timer2 register address: 004ch read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (iclr2) timer1 register address: 003dh timer2 register address: 004dh read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb table 10. 16-bit timer register map and reset values address (hex.) register name 76543210 timer1: 32 timer2: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer1: 31 timer2: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer1: 33 timer2: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer1: 34 timer2: 44 ichr1 reset value msb - ------ lsb - timer1: 35 timer2: 45 iclr1 reset value msb - ------ lsb - timer1: 36 timer2: 46 ochr1 reset value msb - ------ lsb - timer1: 37 timer2: 47 oclr1 reset value msb - ------ lsb - L9803 on-chip peripherals 61/126 5.3 pwm generator 5.3.1 introduction this pwm peripheral includes a 16-bit pulse width modulator (pwm) and a programmable prescaler able to generate an internal clock with period as long as 128*t cpu . the repetition rate of the 16-bit pwm output can be defined by a dedicated register (f cpu /cyreg); its resolution is defined by the internal clock as per the prescaler programming. main features ? programmable prescaler: f cpu divided by 2, 4, 8, 16, 32, 64 or 128. ? 1 control register ? 2 dedicated 16-bit register s for cycle and duty control ? 1 dedicated maskable interrupt procedure to use the pulse width modulation peripheral, the en_pwm bit in conreg register must be set. load ps(2:0) in conreg register to define the programmable prescaler. load the cyreg register with the value defining the cycle length (in internal clock periods). the 16 bits of this register are separated in two registers: cyregh and cyregl. timer1: 3e timer2: 4e ochr2 reset value msb - ------ lsb - timer1: 3f timer2: 4f oclr2 reset value msb - ------ lsb - timer1: 38 timer2: 48 chr reset value msb 1111111 lsb 1 timer1: 39 timer2: 49 clr reset value msb 1111110 lsb 0 timer1: 3a timer2: 4a achr reset value msb 1111111 lsb 1 timer1: 3b timer2: 4b aclr reset value msb 1111110 lsb 0 timer1: 3c timer2: 4c ichr2 reset value msb - ------ lsb - timer1: 3d timer2: 4d iclr2 reset value msb - ------ lsb - table 10. 16-bit timer register map and reset values (continued) address (hex.) register name 76543210 on-chip peripherals L9803 62/126 load the dutyreg register with the value corresponding to the pulse length (in internal cycle periods). the 16 bits of this register are separated in two registers: dutyregh and dutyregl. the counter is reset to zero when en_pwm bit is reset. writing the dutyreg and cyreg registers has no effect on the current pwm cycle. the cycle or duty cycle change take place only after the first overflow of the counter. the suggested procedures to change the pwm parameters are the following: duty cycle control: ? write the low and high dutyreg registers. a writing only on one dutyreg register has no effect until both registers are written. the current pwm cycle will be completed. th e new duty cycle will be effective at the following pwm cycle, with respect to the last dutyreg writing. cycle control: ? write the low and high cyreg register a writing only on one cyreg register has no effect until both registers are written. the current pwm cycle will be completed. the new cycle will be effective at the following pwm cycle, with respect to the last cyreg writing. another possible procedure is: ? reset the en_pwm bit. ? write the wanted configuration in cyreg and dutyreg.. ? set the en_pwm bit. if the en_pwm bit is set after being reset, the current values of dutyreg and cyreg are determining the output waveform, no matter if only the low or the high part, or both were written. the first time en_pwm is set, if cyreg and dutyreg were not previously written, the output is permanently low, because the default value of the registers is 00h. changing the prescaler ratio writing ps(2:0) in conreg has immediate effect on the waveform frequency. 5.3.2 functional description the pwm module consists of a 16-bit counter, a comparator and the cycle generation logic. pwm generation the counter increments continuously, clocked at internal clock generated by prescaler. whenever the 16 bits of the counter (defined as the pwm counter) overflow, the output level is set. the overflow value is defined by cyreg register. the state of the pwm counter is continuously compared to the pwm binary weight, as defined in dutyreg register, and when a match occurs the output level is reset. L9803 on-chip peripherals 63/126 figure 29. pwm cycle note: if the cyreg value is minor or equal than dutyreg value, pwm output remains set. with a dutyreg value of 0000h, the pwm output is permanently at low level, no matter of the value of cyreg. with a dutyreg value of ffffh, the pwm output is permanently at high level. interrupt request the en_int bit in conreg register must be set to enable the interrupt generation. when the 16 bits of the counter roll-over cyclereg value, interrupt request is set. the interrupt request is cleared when any of the pwm registers is written. figure 30. pwm generation 5.3.3 register description the pwm is associated with a 8-bit control registers, and with two 16-bit data registers, each split in two 8-bit registers. pwm cycle register low (cyregl) pwm1 register address: 0011h pwm2 register address: 0019h read/write reset value: 0000 0000 (00h) counter counter is reset out pwm = 1 counter = cyreg out pwm = 0 when when = dutyreg pulse width modulation cycle counter cyreg compare value 000 t pwm output t t (internal clock) x cyreg_value value interrupt generation on-chip peripherals L9803 64/126 this is an 8-bit register that contains the low part of the value to be multiplied by internal clock period. pwm cycle register high (cyregh) pwm1 register address: 0010h pwm2 register address: 0018h read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the high part of the value to be multiplied by internal clock period. . pwm dutycycle register low (dutyregl) pwm1 register address: 0013h pwm2 register address: 001bh read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value corresponding to the binary weight of the pwm pulse. pwm dutycycle register high (dutyregh) pwm1 register address: 0012h pwm2 register address: 001ah read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the high part of the value corresponding to the binary weight of the pwm pulse . pwm control register (conreg) pwm1 register address: 0014h pwm2 register address: 001ch 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb L9803 on-chip peripherals 65/126 read/write reset value: 0000 0000 (00h) bit 0= en _pwm : 1 = enables the pwm output, 0 = disables pwm output. bit 1= en _int : 1 = enables interrupt request, 0 disables interrupt request. bit 4, 3, 2= ps2 , ps1 , ps0 : prescaler bits the value of the pwm internal clock depends on these bits. bit 5, 6, 7= not used. pwm counter register low (ctl) pwm1 register address: 0016h pwm2 register address: 001eh read only reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the pwm counter value. pwm counter register high(cth) pwm1 register address: 0015h pwm2 register address: 001dh read only reset value: 0000 0000 (00h) this is an 8-bit register that contains the high part of the pwm counter value. 7 43210 0 0 0 ps2 ps1 ps0 en_ int en_ pwm ps2 ps1 ps0 pwm internal clock 000 f cpu 001 f cpu / 2 010 f cpu / 4 011 f cpu / 8 100 f cpu / 16 101 f cpu / 32 110 f cpu / 64 111 f cpu / 128 7 0 msb lsb on-chip peripherals L9803 66/126 figure 31. pwm block diagram 7 0 msb lsb table 11. pwm timing (f cpu = 8mhz) prescaler (ps) t internal clock cyreg @16 bit resolution pwm cycle @ f in =8mhz 01/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 0.125 s..... ~8192 s 11/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 0.25 s....... ~16384 s 21/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 0.5 s......... ~32768 s 31/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 1 s............ 65535 s 41/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 2 s............ 131070 s 51/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 4 s............ 262140 s 61/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 8 s............ 524280 s 71/f in * 2 ps 1/f in * 2 ps * 1.....1/f in * 2 ps * 65535 16 s.......... 1048560 s data bus cyreg dutyreg conreg | . | . | . | ps1 | ps2 | ps3 | en_int | en_pwm | clock 7 6 5 4 3 2 1 3 16-bit counter comparator2 comparator1 logic irq pwm 16 16 2 m u x L9803 on-chip peripherals 67/126 5.4 pwm i/o 5.4.1 introduction the pwm i/o interface is a circuit able to conn ect internal logic circuits with external high voltage lines. the two interfaces represent respectively the receiver and the transmitter section of a standard is0 9141 transceiver. connecting pwmo and pwmi together a standard k bus (iso 9141) can be realized. voltage thresholds are referred to the battery voltage connected to vbr pin. this pin must be used as reference for the k bus. voltage drops between this pin and the battery line can cause thresholds mismatch between the L9803 iso trasceiver and the counterpart trasceiver(s) connected to the same bus line. see figure 32 for a block diagram description of the two interfaces. figure 32. pwm i/o block diagram 5.4.2 pwmo pwmo is an output line, directly driven by the pwm2 output signal. the circuit translates the logic levels of pwm2 output to voltage levels referred to the vb supply (see figure 32 ). when pwm2=0 the open drain is switched off, in the other case the pwmo line is pulled down by the open drain driver. pwmo is protected against short circuit to ba ttery by a dedicated circuit that limits the current sunk by the output transistor. when th e limiter is activated the voltage on pwmo pin rises up. if the limiter remains active for more than 25 s the driver is switched off. if the battery or ground connection are lost, the pwmo line shows a controlled impedance characteristic (see figure 33 ). pwm0 is high at nreset is asserted. vdd pwmo vdd timer capture input pwm2 output pb2 register bit - + pwmi vbr battery k bus on-chip peripherals L9803 68/126 figure 33. impedance at pwmo/i pin 5.4.3 pwmi pwmi is an input line, directly connected to pb2 bit. the circuit translates the voltage levels referred to vb voltage supply to the internal logic levels (see figure 32 ). when the voltage on pwmi pin is higher than vb/2 pb2 reads an high logic level. if the bit pwmi in dcsr register is set (see section 3.2.1 ), pwmi is directly connected with the input capture 2 on timer 2, which is otherwise connected in alternate function to pa7 (see figure 34 ). an internal pull down current generator (5a ) allows to detect the open bus condition (external pull up missing). if the battery or ground connection are lost, the pwmi line shows a controlled impedance characteristic (see figure 34 ). figure 34. pwmi function describe the register dcsr (0022h) as reported in table 1. 50k ? 50k ? 5 a v k i k 14v 0 1 timer 2 icap2 pien dcsr pwm i/o m u x pwm input pa(7) alternate input port pwmi pa7 pa(7) pb(2) .............. ..... L9803 on-chip peripherals 69/126 5.5 10-bit a/d converter (ad10) 5.5.1 introduction the analog to digital converter is a single 10-bit successive approximation converter with 4 input channels. analog voltage from external sources are input to the converter through ad2,ad3 and ad4 pins. channel 1 (ad1) is con nected to the internal temperature sensor (see section 5.5.5 ). note: the anti aliasing filtering must be accomplished using an external rc filter. the internal ad1 channel is filtered by an rc network with approx. 1 s time constant. 5.5.2 functional description the result of the conversion is stored in 2 registers: the da ta register high (adcdrh) and the data register low (adcdrl). the a/d converter is enabled by setting the adst bit in adccsr register. bits ch1 and ch0 of adccsr register select the channel to be converted. the hi gh and low reference voltage are connected to pins vcc and agnd. when enabled, the a/d converter performs a complete conversion in 14 s (with system clock f cpu =8mhz). the total conversion time incl udes multiplex, sampling of the input voltage, 10-bit conversion and writing drh and drl registers. when the conversion is completed coco bit (conversion completed) is set in adccsr. a conversion starts from the moment adst bit is set. when a conversion is running it is possible to write the adccsr without stopping the adc operations, because all the data in adccsr are latched when adst is set. this property allows to select a different channel to be processed during the next conversion or to manage the interrupt enable bit. the new setting will have effect on the next conv ersion (including inte rrupt generation) at the end of the conversion adst is reset and coco bit is set. note: to start a new conversion the adst must be set after the completion of the current one. any writing to adst when a conversion is running (coco=0) has no effect since adst bit is automatically reset by the end of conversion event. on-chip peripherals L9803 70/126 figure 35. block diagram of the analog to digital converter 5.5.3 input selections and sampling the input section of the adc includes the analog multiplexer and a buffer. the input of the buffer is permanently connected to the multiplexer output. the buffer output is fed to the sample and hold circuit. the multiplexer is driven with ch1 and ch0 bit on ly after adst is set. starting from this event, the sampler follows the selected input signal for 2.5us and then holds it for the remaining conversion time (i.e. when the conversion is actually running). 5.5.4 interrupt management if adie bit is set in register adccsr, an interrupt is generated when a conversion is completed (i.e. when coco is set). the interrupt request is cleared when any of the adc registers is access (either read or write). enabling/disabling the interrupt generation while the conversion is running has no effect on the current conversion. adie value is latched wh en adst is set and this internal value holds all the conversion time long. 5.5.5 temperature sensing the ad1 input is internally connected to the output of a temperature sensing circuit. ch0 ch1 adst logic u x m d i v clk 8mhz 2 mhz start conversion ..... ad0 ad9 drh drl end conversion wr vin vcc agnd inputs csr sampling + conversion latch adie L9803 on-chip peripherals 71/126 the sensor generates a voltage proportional to the absolute temperature of the die. it works over the whole temperature range, with a minimum resolution of 1lsb/k (5mv/k) ( figure 36 shows the indicative voltage output of the sensor). note the voltage output of the sensor is only related to the absolute temperature of the silicon junctions. junction tem perature and ambient te mperature must be related taking in account the power dissipated by the device and the thermal resistance rth je between the silicon and the environment ar ound the applic ation board. figure 36. temperature sensor output the output of the sensor is not ratiometric with the voltage reference for the adc conversion (vcc). when calculating the adc reading error of this signal the variation of vcc must be accounted. additional errors are due to the intrinsic spread of the sensor characteristic. 5.5.6 precise temperature measurement to allow a more precise measurement of the temperature a trimming procedure can be adopted (on request). the temperature is me asured in ews and two values are stored in four eeprom bytes (see memory map): t0l,t0h: temperature of the trimming measurement (in kelvin). vt0l,vt0h: output value of the adc corresponding to t0 (in number of lsbs). the corrected measurement of the temperature in kelvin must be accomplished in the following way: temp (in k) = vtemp * t0 / vt0 where vtemp is the output code in lsb of the adc corresponding to the measurement. example: if the value stored in eeprom are: 0c7ch: 01h ->t0h 0c7dh: 43h ->t0l 0c7eh: 01h -> vt0h 0c7fh: 5ch -> vt0l v temp temperature (k) 1.0 2.5 1.3 1.6 1.9 2.2 273 323 373 423 473 223 max min on-chip peripherals L9803 72/126 t0 = 0143h = 323k (50 celsius) vto = 015ch = 348 lsb (conversion of 1.7v, sensor output) and the sensor output is 2v, converted by the adc in code 0110011001 = 019ah = 410lsb, the temperature of the chip is temp = 019ah * 0143h / 015ch = 017ch equivalent to: temp = 410 * 323 / 348 = 380 k = 107 c note: the sensor circuit may have two kind of erro r: one translating its output characteristic up and down and the other changing its slope. the described trimming recovers only the translation errors but can not recover slope error. after trimming, being t trim the trimming temperature, the specified precision can be achieved in the range t trim -80, max[t trim +80, 150 c]. precision is related to the read temperature in kelvin. 5.5.7 register description control/status re gister (adccsr) address: 0072h ? read/write reset value: 0010 0000 (20h) bit 7,6 = reserved bit 5 = coco (read only) conversion complete coco is set (by the adc) as soon as a conv ersion is completed (results can be read). coco is cleared by setting adst=1 (start of new conversion). if coco=0 a conversion is running, if coco=1 no conversion is running. bit 4 = adie a/d interrupt enable this bit is used to enable / disable the interrupt function: 0: interrupt disabled 1: interrupt enabled bit 3= reserved bit 2= adst start conversion when this bit is set a new conversion starts. adst is automatically reset when the conversion is completed (coco=1). bits 1-0 = ch1-ch0 channel selection these bits select the analog input to convert. see ta b l e 1 2 for reference. 7 0 0 0 coco adie 0 adst ch1 ch0 L9803 on-chip peripherals 73/126 data register high (adcdrh) address: 0070h ? read only reset value: 00000 0000 (00h) bit 1:0 = ad9-ad8 analog converted value this register contains the high part of the converted analog value data register low (adcdrl) address: 0071h ? read only reset value: 00000 0000 (00h) bit 7:0 = ad7-ad0 analog converted value this register contains the low part of the converted analog value table 12. adc channel selection table ch1 ch0 channel 0 0 ad1, temperature sensor 0 1 ad2, external input 1 0 ad3, external input 1 1 ad4, external input 7 0 000000ad9ad8 7 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 on-chip peripherals L9803 74/126 5.6 controller area network (can) 5.6.1 introduction this peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in can specification rev. 2.0 part a. it can also be connected to a 2.0 b network without problems, since extended frames are checked for correctness and acknowledged accordingly although such frames cannot be transmitted nor received. the same applies to overload fram es which are recognized but never initiated. figure 37. can block diagram tx/rx buffer 1 10 bytes tx/rx buffer 2 10 bytes tx/rx buffer 3 10 bytes id filter 0 4 bytes id filter 1 4 bytes st7 interface psr icr isr brpr csr tecr recr can 2.0b passive core shreg bcdl crc btl rx tx eml st7 internal bus btr L9803 on-chip peripherals 75/126 5.6.2 main features support of can specification 2.0a and 2.0b passive three prioritized 10-byte transmit/receive message buffers two programmable global 12-bit message acceptance filters programmable baud rates up to 1 mbit/s buffer flip-flopping ca pability in transmission maskable interrupts for transmit, receive (one per buffer), error and wake-up automatic low-power mode after 20 recessive bits or on demand (standby mode) interrupt-driven wake-up from standby mode upon reception of dominant pulse optional dominant pulse transmission on leaving standby mode automatic message queuing for transmission upon writing of data byte 7 programmable loop-back mode for self-test operation advanced error detection and diagnosis functions software-efficient buffer mapping at a unique address space scalable architecture. 5.6.3 functional description frame formats a summary of all the can frame formats is given in figure 38 for reference. it covers only the standard frame format since the extended one is only acknowledged. a message begins with a start bit called start of frame (sof). this bit is followed by the arbitration field which contains the 11-bit i dentifier (id) and the remote transmission request bit (rtr). the rtr bit indicates whether it is a data frame or a remote request frame. a remote request frame does not have any data byte. the control field contains the identifier exte nsion bit (ide), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (dlc). the data field ranges from zero to eight bytes and is followed by the cyclic redundancy check (crc) used as a frame integrity check for detecting bit errors. the acknowledgement (ack) field comprises the ack slot and the ack delimiter. the bit in the ack slot is placed on the bus by the trans mitter as a recessive bit (logical 1). it is overwritten as a dominant bit (logical 0) by th ose receivers which have at this time received the data correctly. in this way, the transmitting node can be assured that at least one receiver has correctly received its message. note that messages are acknowledged by the receivers regardless of the outcome of the acceptance test. the end of the message is indicated by the end of frame (eof). the intermission field defines the minimum number of bit periods separating consecutive messages. if there is no subsequent bus access by any st ation, the bus remains idle. on-chip peripherals L9803 76/126 hardware blocks the can controller contains the following functional blocks (refer to figure 37 ): st7 interface: buffering of the st7 internal bus and address decoding of the can registers. tx/rx buffers: three 10-byte buffers for transmission and reception of maximum length messages. id filters: two 12-bit compare and don?t care masks for message acceptance filtering. psr: page selection register (see memory map). brpr: clock divider for different data rates. btr: bit timing register. icr: interrupt control register. isr: interrupt status register. csr: general purpose control/status register. tecr: transmit error counter register. recr: receive error counter register. btl: bit timing logic providing programmable bit sampling and bit clock generation for synchronization of the controller. bcdl: bit coding logic generating a nrz-coded datastream with stuff bits. shreg: 8-bit shift register for serialization of data to be transmitted and parallelisation of received data. crc: 15-bit crc calculator and checker. eml: error detection and management logic. can core: can 2.0b passive protocol controller. L9803 on-chip peripherals 77/126 figure 38. can frames modes of operation the can core unit assumes one of the seven states described below: standby . standby mode is entered either on a chip reset or on resetting the run bit in the control/status register (csr). any on-going transmission or reception operation is not interrupted and completes normally before the bit time logic and the clock prescaler are turned off for minimum power consumption. this state is signalled by the data field 8 * n control field 6 arbitration field 12 crc field 16 ack field 7 sof id dlc crc data frame 44 + 8 * n arbitration field 12 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc control field 6 overload flag 6 overload delimiter 8 overload frame error flag 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame data frame or remote frame notes: 0 <= n <= 8 sof = start of frame id = identifier rtr = remote transmission request ide = identifier extension bit r0 = reserved bit dlc = data length code crc = cyclic redundancy code error flag: 6 dominant bits if node is error active else 6 recessive bits. suspend transmission: applies to error passive nodes only. eof = end of frame ack = acknowledge bit data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field end of frame rtr ide r0 eof on-chip peripherals L9803 78/126 run bit being read-back as 0. once in standby, the only event monitored is the reception of a dominant bit which causes a wake-up interrupt if the scie bit of the interrupt control register (icr) is set. the standby mode is left by setting the run bit. if the wkps bit is set in the csr register, then the controller passes thro ugh wake-up otherwise it enters resync directly. it is important to note that the wake-up mechanism is software-driven and therefore carries a significant time overhead. all messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. wake-up . the can bus line is forced to dominant for one bit time signalling the wake- up condition to all other bus members. figure 39. can contro ller state diagram n resync . the resynchronization mode is used to find the correct entry point for starting transmission or reception after the node has gone asynchronous either by going into the standby or bus-off states. resynchronization is achieved when 128 se quences of 11 recessive bits have been standby resync wake-up reception transmission error idle areset run run & wkps run & wkps fsyn & boff & 11 recessive bits | (fsyn | boff) & 128 * 11 recessive bits run write to data7 | tx error & nrtx start of frame arbitration lost tx error rx error tx ok rx ok boff boff L9803 on-chip peripherals 79/126 monitored unless the node is not bus-off and the fsyn bit in the csr register is set in which case a single sequence of 11 recessive bits needs to be monitored. idle . the can controller looks for one of the following events: the run bit is reset, a start of frame appears on the can bus or the data7 register of the currently active page is written to. transmission . once the lock bit of a buffer control/status register (bcsrx) has been set and read back as such, a transmit job can be submitted by writing to the data7 register. the message with the highes t priority will be transmitted as soon as the can bus becomes idle. among those messages with a pending transmission request, the highest priority is given to buffer 3 then 2 and 1. if the transmission fails due to a lost arbitration or to an error while the nrtx bit of the csr register is reset, then a new transmission attempt is performed . this goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by setting the nrtx bit or if the node ever enters bus-off or if a higher priority message becomes pending. the rdy bit in the bcsrx register, which was set since the job was submitted, gets reset. when a transmission is in progress, the busy bit in the bcsrx register is set. if it ends successfully then the txif bit in the interrupt status register (isr) is set, else the teif bit is set. an interrupt is generated in either case provided the txie and teie bits of the icr register are set. the etx bit in the same register is used to get an early transmit interrupt and to automatically unlock the transmitting buffer upon successful completion of its job. this enables the cpu to get a new transmit job pending by the end of the current transmission while always leaving two buffers available for reception. an uninterrupted stream of messages may be transmitted in this way at no overrun risk. note 1: setting the srte bit of the csr register allows transmitted messages to be simultaneously received when they pass the acc eptance filtering. this is particularly useful for checking the integrity of the communication path. note 2: when the etx bit is reset, the buffer with the highest priority and with a pending transmission request is always transmitted. when the etx bit is set, once a buffer participates in the arbitration phase, it is sent until it wins the arbitration even if another transmission is requested from a buffer with a higher priority. reception . once the can controller has synchronized itself onto the bus activity, it is ready for reception of new messages. every incoming message gets its identifier compared to the acceptance filters. if the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. this buffer will be the first one - order is 1 to 3 - that has the lock and rdy bits of its bcsrx register reset. ? when no such buffer exists then an overrun interrupt is generated if the orie bit of the icr register has been set. in this case the identifier of the last message is made available in the last identifier register (lidhr and lidlr) at least until it gets overwritten by a new identifier picked-up from the bus. ? when a buffer does exist, the accepted message gets written into it, the acc bit in the bcsrx register gets the number of the matching filter, the rdy and rxif bits get set and an interrupt is generated if the rxie bit in the isr register is set. up to three messages can be automatically received without intervention from the cpu because each buffer has its own set of stat us bits, greatly reducing the reactiveness requirements in the processing of the receive interrupts. error . the error management as described in the can protocol is completely handled by hardware using 2 error counters which get incremented or decremented according to the error condition. both of them may be read by the application to on-chip peripherals L9803 80/126 determine the stability of the network. more over, as one of the node status bits (epsv or boff of the csr register) changes, an interrupt is generated if the scie bit is set in the icr register. refer to figure 40 . figure 40. can error state diagram bit timing logic the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on following edges. its operation may be explained simply when the nominal bit time is divided into three segments as follows: synchronisation segment (sync_seg) : a bit change is expected to lie within this time segment. it has a fixed length of one time quanta (1 x t can ). bit segment 1 (bs1) : defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can standard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network. bit segment 2 (bs2) : defines the location of the transmit point. it represents the phase_seg2 of the can standard. its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts. resynchronization jump width (rjw) : defines an upper bound to the amount of lengthening or shortening of the bit segments. it is programmable between 1 and 4 time quanta. to guarantee the correct behaviour of the can controller, sync_seg + bs1 + bs2 must be greater than or equal to 5 time quanta. for a detailed description of the can resynchronization mechanism and other bit timing configuration constraints, please refer to the can specification - bosh - version 2. error passive when tecr or recr > 127, the epsv bit gets set when tecr and recr < 128, and the epsv bit gets cleared error active bus off when tecr > 255 the boff bit gets set when 128 * 11 recessive bits occur: - the boff bit gets cleared - the tecr register gets cleared - the recr register gets cleared the epsv bit gets cleared L9803 on-chip peripherals 81/126 as a safeguard against programming errors, t he configuration of the bit timing register (btr) is only possible while the device is in standby mode. figure 41. bit timing 5.6.4 register description the can registers are organized as 6 general purpose registers plus 5 pages of 16 registers spanning the same address space and primarily used for message and filter storage. the page actually selected is defined by the content of the page selection register. refer to figure 42 . general purpose registers interrupt status register (isr) read/write reset value: 00h bit 7 = rxif3 receive interrupt flag for buffer 3 ? read/clear set by hardware to signal that a new error-free message is available in buffer 3. cleared by software to release buffer 3. also cleared by resetting bit rdy of bcsr3. bit 6 = rxif2 receive interrupt flag for buffer 2 ? read/clear set by hardware to signal that a new error-free message is available in buffer 2. cleared by software to release buffer 2. also cleared by resetting bit rdy of bcsr2. bit 5 = rxif1 receive interrupt flag for buffer 1 ? read/clear set by hardware to signal that a new error-free message is available in buffer 1. cleared by software to release buffer 1. also cleared by resetting bit rdy of bcsr1. bit 4 = txif transmit interrupt flag ? read/clear set by hardware to signal that the highest priority message queued for transmission has been successfully transmitted (etx = 0) or that it has passed successfully the arbitration sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1 x t can t bs1 t bs2 sample point transmit point 7 0 rxif3 rxif2 rxif1 txif scif orif teif epnd on-chip peripherals L9803 82/126 (etx = 1). cleared by software. bit 3 = scif status change interrupt flag ? read/clear set by hardware to signal the reception of a dominant bit while in standby or a change from error active to error passive and bus-off while in run. also signals any receive error when esci = 1. cleared by software. bit 2 = orif overrun interrupt flag ? read/clear set by hardware to signal that a message could not be stored because no receive buffer was available. cleared by software. bit 1 = teif transmit error interrupt flag ? read/clear set by hardware to signal that an error occurred during the transmission of the highest priority message queued for transmission. cleared by software. bit 0 = epnd error interrupt pending ? read only set by hardware when at least one of the three error interrupt flags scif, orif or teif is set. reset by hardware when all error interrupt flags have been cleared. caution: interrupt flags are reset by writing a "0" to the corresponding bit position. the appropriate way consists in writing an immediate mask or the one?s complement of the register content initially read by the interrupt handler. bit manipulation instruction bres should never be used due to its read-modify-write nature. interrupt control register (icr) read/write reset value: 00h bit 6 = esci extended status change interrupt ? read/set/clear set by software to specify that scif is to be set on receive errors also. cleared by software to set scif only on status changes and wake-up but not on all receive errors. bit 5 = rxie receive interrupt enable ? read/set/clear set by software to enable an interrupt request whenever a message has been received free of errors. cleared by software to disable receive interrupt requests. 7 0 0 esci rxie txie scie orie teie etx L9803 on-chip peripherals 83/126 bit 4 = txie transmit interrupt enable ? read/set/clear set by software to enable an interrupt request whenever a message has been successfully transmitted. cleared by software to disable transmit interrupt requests. bit 3 = scie status change interrupt enable ? read/set/clear set by software to enable an interrupt request whenever the node?s status changes in run mode or whenever a dominant pulse is received in standby mode. cleared by software to disable status change interrupt requests. bit 2 = orie overrun interrupt enable ? read/set/clear set by software to enable an interrupt request whenever a message should be stored and no receive buffer is avalaible. cleared by software to disable overrun interrupt requests. bit 1 = teie transmit error interrupt enable ? read/set/clear set by software to enable an interrupt whenever an error has been detected during transmission of a message. cleared by software to disable transmit error interrupts. bit 0 = etx early transmit interrupt ? read/set/clear set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passe d successfully. cleared by software to request the transmit interrupt to occur at the completion of the transfer. control/status register (csr) read/write reset value: 00h bit 6 = boff bus-off state ? read only set by hardware to indicate that the node is in bus-off state, i.e. the transmit error counter exceeds 255. reset by hardware to indicate that the node is involved in bus activities. bit 5 = epsv error passive state ? read only set by hardware to indicate that the node is error passive. reset by hardware to indicate that the node is either error active (boff = 0) or bus-off. bit 4 = srte simultaneous receive/transmit enable ? read/set/clear set by software to enable simultaneous transmission and reception of a message passing the acceptance filtering. allows to check the integrity of the communication path. 7 0 0 boff epsv srte nrtx fsyn wkps run on-chip peripherals L9803 84/126 reset by software to discard all messages transmitted by the node. allows remote and data frames to share the same identifier. bit 3 = nrtx no retransmission ? read/set/clear set by software to disable the retransmission of unsuccessful messages. cleared by software to enable retransmis sion of messages un til success is met. bit 2 = fsyn fast synchronization ? read/set/clear set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 recessive bits in a row. cleared by software to enable the standard resynchronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits. bit 1 = wkps wake-up pulse ? read/set/clear set by software to generate a dominant pulse when leaving standby mode. cleared by software for no dominant wake-up pulse. bit 0 = run can enable ? read/set/clear set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11 recessive bits if fsyn is set. cleared by software to request a switch to the standby or low-power mode as soon as any on-going transfer is complete. read-back as 1 in the meantime to enable proper signalling of the standby state. the cpu clock may therefore be safely switched off whenever run is read as 0. baud rate prescaler register (brpr) read/write in standby mode reset value: 00h rjw[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization. t rjw = t can * (rjw + 1) brp[5:0] determine the can system clock cycle time or time quanta which is used to build up the individual bit timing. t can = t cpu * (brp + 1) where t cpu = time period of the cpu clock. the resulting baud rate can be computed by the formula: note: writing to this register is allowed only in standby mode to prevent any accidental can protocol violation through programming errors. 7 0 rjw1 rjw0 brp5 brp4 brp3 brp2 brp1 brp0 br 1 t cpu brp 1 + () bs1 bs2 3 ++ () -------------------------------------------------------------------------------------------------- = L9803 on-chip peripherals 85/126 bit timing register (btr) read/write in standby mode reset value: 23h bs2[2:0] determine the length of bit segment 2. t bs2 = t can * (bs2 + 1) bs1[3:0] determine the length of bit segment 1. t bs1 = t can * (bs1 + 1) note: writing to this register is allowed only in standby mode to prevent any accidental can protocol violation through programming errors. page selection register (psr) read/write reset value: 00h page[2:0] determine which buffer or filter page is mapped at addresses 0010h to 001fh. page 0 registers last identifier high register (lidhr) read/write reset value: undefined 7 0 0 bs22 bs21 bs20 bs13 bs12 bs11 bs10 7 0 0 0 0 0 0 page2 page1 page0 pag e 2 pag e 1 page 0 pag e t i tl e 000diagnosis 001buffer 1 010buffer 2 011buffer 3 100filters 101reserved 110reserved 111reserved 7 0 lid10 lid9 lid8 lid7 lid6 lid5 lid4 lid3 on-chip peripherals L9803 86/126 lid[10:3] are the most significant 8 bits of the last identifier read on the can bus. last identifier low register (lidlr) read/write reset value: undefined lid[2:0] are the least significant 3 bits of the last identifier read on the can bus. lrtr is the last remote transmission request bit read on the can bus. ldlc[3:0] is the last data length code read on the can bus. transmit error counter reg. (tecr) read only reset value: 00h tec[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of the fault confinement mechanism of the can protocol. in case of an error during transmission, this counter is incremented by 8. it is decremented by 1 after every successful transmission. when the counter value exceeds 127, the can controller enters the error passive state. when a value of 256 is reached, the can controller is disconnected from the bus. receive error counter reg. (recr) page: 00h ? read only reset value: 00h rec[7:0] is the receive error counter implementing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can standard. after every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. pages 1,2,3 registers identifier high registers (idhrx) 7 0 lid2 lid1 lid0 lrtr ldlc3 ldlc2 ldlc1 ldlc0 7 0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 7 0 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 L9803 on-chip peripherals 87/126 read/write reset value: undefined id[10:3] are the most significant 8 bits of the 11-bit message identifier.the identifier acts as the message?s name, used for bus access arbitration and acceptance filtering. identifier low registers (idlrx) read/write reset value: undefined id[2:0] are the least significant 3 bits of the 11-bit message identifier. rtr is the remote transmission request bit. it is set to indicate a remote frame and reset to indicate a data frame. dlc[3:0] is the data length code. it gives the number of bytes in the data field of the message.the valid range is 0 to 8. data registers (data0-7x) read/write reset value: undefined data[7:0] is a message data byte. up to eight such bytes may be part of a message. writing to byte data7 initiates a transmit request and should always be done even when data7 is not part of the message. buffer control/status regs. (bcsrx) read/write reset value: 00h bit 3 = acc acceptance code ? read only set by hardware with the id of the highest priority filter which accepted the message stored in the buffer. 7 0 id10 id9 id8 id7 id6 id5 id4 id3 7 0 id2 id1 id0 rtr dlc3 dlc2 dlc1 dlc0 7 0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 7 0 0000accrdybusylock on-chip peripherals L9803 88/126 acc = 0: match for filter/mask0. possible match for filter/mask1. acc = 1: no match for filter/mas k0 and match for filter/mask1. reset by hardware when either rdy or rxif gets reset. bit 2 = rdy message ready ? read/clear set by hardware to signal that a new error-free message is available (lock = 0) or that a transmission request is pending (lock = 1). cleared by software when lock = 0 to release the buffer and to clear the corresponding rxif bit in the interrupt status register. cleared by hardware when lock = 1 to indicate that the transmission request has been serviced or cancelled. bit 1 = busy busy buffer ? read only set by hardware when the bu ffer is being filled (lock = 0) or emptied (lock = 1). reset by hardware when the buffer is not accessed by the can core for transmission nor reception purposes. bit 0 = lock lock buffer ? read/set/clear set by software to lock a buffer. no more message can be received into the buffer thus preserving its content and making it available for transmission. cleared by software to make the buffer available for reception. cancels any pending transmission request. cleared by hardware once a message has been successfully transmitted provided the early transmit interrupt mode is on. left untouched otherwise. note that in order to prevent any message corruption or loss of context, lock cannot be set nor reset while busy is set. trying to do so will result in lock not changing state. pages 4 registers filter high registers (fhrx) read/write reset value: undefined fil[11:4] are the most significant 8 bits of a 12-bit message filter. the acceptance filter is compared bit by bit with the identifier and the rtr bit of the incoming message. if there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. filter low registers (flrx) read/write reset value: undefined 7 0 fil11 fil10 fil9 fil8 fil7 fil6 fil5 fll4 7 0 fil3 fil2 fil1 fil0 0 0 0 0 L9803 on-chip peripherals 89/126 fil[3:0] are the least significant 4 bits of a 12-bit message filter. mask high registers (mhrx) read/write reset value: undefined msk[11:4] are the most significant 8 bits of a 12-bit message mask. the acceptance mask defines which bits of the acceptance filter should match the identifier and the rtr bit of the incoming message. msk i = 0: don?t care. msk i = 1: match required. mask low registers (mlrx) read/write reset value: undefined msk[3:0] are the least significant 4 bits of a 12-bit message mask. 7 0 msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 7 0 msk3 msk2 msk1 msk0 0 0 0 0 on-chip peripherals L9803 90/126 figure 42. can register map interrupt status interrupt control control/status baud rate prescaler page selection paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg0 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 6fh 5ch 5ah 5bh 5dh 5fh 60h bit timing 5eh L9803 on-chip peripherals 91/126 figure 43. page maps 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh fhr0 flr0 mhr0 mlr0 fhr1 flr1 mhr1 mlr1 reserved idhr1 idlr1 data01 data11 data21 data31 data41 data51 data61 data71 reserved bcsr1 lidhr lidlr reserved tstr tecr recr idhr2 idlr2 data02 data12 data22 data32 data42 data52 data62 data72 reserved bcsr2 idhr3 idlr3 data03 data13 data23 data33 data43 data53 data63 data73 reserved bcsr3 page 0 page 1 page 2 page 3 page 4 diagnosis buffer 1 buffer 2 buffer 3 acceptance filters table 13. can register map and reset values address (hex.) page register label 7 6 543210 5a canisr reset value rxif3 0 rxif2 0 rxif1 0 txif 0 scif 0 orif 0 teif 0 epnd 0 5b canicr reset value 0 esci 0 rxie 0 txie 0 scie 0 orie 0 teie 0 etx 0 5c cancsr reset value 0 boff 0 epsv 0 srte 0 nrtx 0 fsyn 0 wkps 0 run 0 5d canbrpr reset value rjw1 0 rjw0 0 brp5 0 brp4 0 brp3 0 brp2 0 brp1 0 brp0 0 5e canbtr reset value 0 bs22 0 bs21 1 bs20 0 bs13 0 bs12 0 bs11 1 bs10 1 5f canpsr reset value 0 0 0 0 0 pag e 2 0 pag e 1 0 pag e 0 0 60 0 canlidhr reset value lid10 x lid9 x lid8 x lid7 x lid6 x lid5 x lid4 x lid3 x 1 to 3 canidhrx reset value id10 x id9 x id8 x id7 x id6 x id5 x id4 x id3 x 60, 64 4 canfhrx reset value fil11 x fil10 x fil9 x fil8 x fil7 x fil6 x fil5 x fil4 x on-chip peripherals L9803 92/126 5.7 can bus transceiver 5.7.1 introduction the can bus transceiver allows the connection of the microcontroller, with can controller unit, to a can bus. the transmitter section dr ives the can bus while the receiver section senses the data on the bus. the can transceiver meets iso/dis 11898 up to 1 mbaud. 5.7.2 main features transmitter: generation of differential output signals short circuit protection from transients in automotive environment slope control to reduce rfi and emi high speed (up to 1mbaud) if un-powered, L9803 can node does not disturb the bus lines (the transceiver is in recessive state). receiver: differential input with high interference suppression common mode input voltage range (v com ) from -5 to 12v 61 0 canlidlr reset value lid2 x lid1 x lid0 x lrtr x ldlc3 x ldlc2 x ldlc1 x ldlc0 x 1 to 3 canidlrx reset value id2 x id1 x id0 x rtr x dlc3 x dlc2 x dlc1 x dlc0 x 61, 65 4 canflrx reset value fil3 x fil2 x fil1 x fil0 x0000 62 to 69 1 to 3 candrx reset value msb xxxxxxx lsb x 62, 66 4 canmhrx reset value msk11 x msk10 x msk9 x msk8 x msk7 x msk6 x msk5 x msk4 x 63, 67 4 canmlrx reset value msk3 x msk2 x msk1 x msk0 x0000 6e 0 cantecr reset value msb 0000000 lsb 0 6f canrecr reset value msb 0000000 lsb 0 1 to 3 canbcsrx reset value 0 0 0 0 acc 0 rdy 0 busy 0 lock 0 table 13. can register map and reset values (continued) address (hex.) page register label 7 6 543210 L9803 on-chip peripherals 93/126 5.7.3 functional description the can bus transceiver is used as an interface between a can controller and the physical bus. the device provides transmitting capabilit y to the can controller. the transceiver has one logic input pin (tx), one logic output pin (rx) and two input/output pins for the electrical connections to the two bus wires (can_l and can_h). the microcontroller sends data to the tx pin and it receives data from the rx pin. the transmission slew-rates of can_h and can_l voltage are controlled to reduce rfi and emi. the transceiver is protected against short circuit or overcurrent: if i canh and/or i canl exceeds a current thresholds i sc , then the can_h and can_l power transistors are switched off and the transmission is disabled for t d =25 s typical. 5.7.4 can transceiver disabling function the transceiver can be disabled and forced to move in a low power consumption mode, setting cands bit in dcsr register. when the transceiver is in this mode it can not receive nor transmit any information to the bus. the only way to have again on board the can capabilities is reset cands bit. the can pr otocol handler can not disable nor enable the transceiver and there is no way to communicate to the controller the transceiver is down. the disabling function has the only purpose to allow the reduction of the current consumption of the device in application not using the can at all or using it for particular functions (such like debugging). current consumption reduction, when disabling the trasceiver, can be as high as 15ma. note when the can capabilities of L9803 are not needed additional consumption reduction can be achieved putting the can controller in stand-by mode. figure 44. can bus transceiver block diagram 5.8 power bridge 5.8.1 introduction the power part of the device consists of two identical independent dmos half bridges. it is suited to drive resistive and inductive loads. ?? + ? tx0 rx0 can_h can_l overcurrent detection overcurrent detection power control r 2r r rr 2r vdd gnd on-chip peripherals L9803 94/126 5.8.2 main features the nominal current is 2a. the low-side switch is a n-channel dmos tr ansistor while the high-side switch is a p- channel dmos transistor. therefore no charge pump is needed. an anti-crossconduction circuit is included: the low side dmos is switched on only when the high side is switched off and vice versa. this function avoid the two dmos are switched on together firing the high current path from battery to ground. the function is obtained by sensing the gate voltage and therefore the delay between command and effective switch on of the dmos doesn?t have a fixed length. the mcu controls all operations of the power stage through the bcsr dedicated register. short circuit and overtemperature conditions are reported to the cpu using dedicated error flags. overtemperature and short circuit conditions switch off the bridge immediately without cpu intervention. the function of the flags is independent of the operation mode of the bridge (sink, source, z). in addition both the pwm modules can be directly connected to the power bridge. the power bridge offers then many driving mode alternatives: direct mode : the two half bridges are directly driven by in1 and in2 control bit in bcsr. pwm1 up/down brake mode : the output of pwm1 drives one side of the bridge while the other side is maintained in a fixed status. pwm1 symmetrical driving mode : pwm1 line drives directly and symmetrically both side of the bridge. pwm1/pwm2 mode : pwm1 drives one side while pwm2 drives the other (two independent half bridges). 5.8.3 functional description a schematic description of the power bridge circuit is depicted in figure 45 . in this schematic the transistors must be considered in on condition when they gate is high (set). L9803 on-chip peripherals 95/126 figure 45. power bridge schematic en bit in bcsr is the main enable signal, active high. if en = 0, all the bridge transistors are switched off (ul, ur, dl and dr are reset) and the outputs outl and outr are in high impedance state. being '0' the status after reset of en, the bridge is in safe condition (outl=outr=z). therefore the safe condition is guaranteed in undervoltage condition (lvd reset) and in case of main clock (safeguard reset) or software (watchdog reset) failures. each power dmos has its own over current de tector circuit generating sc_xx signals (see figure 45 ). sc_xx signals are ored together to generate sc flag in bcsr register. sc flag is then set by hardware as soon as one of the two outputs (or both) are short to battery, ground or if the two outputs are short together (load short). this read only bit is reset only by clearing the en bit. the rising edge of sc causes an interrupt request if the pie bit is set in bcsr register. when the current monitored in any of the four dmos of the bridge exceeds limit threshold (i sc ), the sc bit is set and the corresponding dmos is switched off after t scpi time. this function is dominant over any write from data bus by software (i. e. as long as sc is set, the bridge cannot be switched on). to switch the bridge on again the en bit must be cleared by software. this resets the sc bit. setting again en, the bridge is switched on. if the over current condition is still present, sc is set again (and a interrupt is generated when enabled). an internal thermal protection circuit monitors continuously the temperature of the device and drives the ovt bit in bcsr register and, in turn, the ovt signal in figure 45 . the ovt flag is set as soon as the temperature of the chip exceeds thw and all the transistor of the bridge are switched off. this rising edge causes an interrupt request if the pie bit is set. this read only bit is reset only by clearing the en bit. this function is dominant over any write from data bus by software (i. e. as long as ovt is set the bridge cannot be switched on). to switch the bridge on again the en bit must be cleared by software. this resets the ovt bit. setting again en, the bri dge is switched on. if the overtemperature condition is still present, ovt is set again (and a interrupt is generated when enabled). vbr pgnd outr vbl pgnd outl ul ur dl dr sc_ul ovt sc_dl ovt sc_dr ovt sc_ur ovt on-chip peripherals L9803 96/126 5.8.4 interrupt generation interrupt generation is controlled by pdie bit in bcsr register. when this bit is set overtemperature and short-circuit conditions generate an interrupt as described in section 5.6.3 . setting pdie when sc and/or ovt flag are set, immediately generates an interrupt request. the interrupt request of the power bridge is cleared when the en bit is cleared by software. 5.8.5 operating modes the status of the outl and outr power outputs is controlled by in1, in2, en, pwm_en and dir bit in bcsr register, plus the pwm1 and pwm2 line, according to the functional description table ( ta bl e 1 4 ). note: the functional description table ( ta bl e 1 4 ) uses symbols ul,r (up left or right) and dr,l (down left or right) to indicate the driving signal of the four dmos. conventionally a transistor is in the on status when its driving signal is set (?1?) while it is in off status when the driving signal is reset (?0?). L9803 on-chip peripherals 97/126 table 14. functional description table drive en pwm_en dir pwm1 in1 in2 ul dl ur dr operation configuration 0 x xxxx0000 inhibit direct mode 1 0 x x 0 0 0 1 0 1 brake full or tw o h a l f bridges 1 0 xx010110 back full or tw o h a l f bridges 1 0 xx101001 forward full or tw o h a l f bridges 1 0 x x 1 1 1 0 1 0 brake full or tw o h a l f bridges pwm1 up brake mode 1 1 0 0 0 0 1 0 1 0 brake full bridge 1 1 0 1 0 0 1 0 0 1 forward full bridge 1 1 1 0 0 0 1 0 1 0 brake full bridge 1 1 1 1 0 0 0 1 1 0 back full bridge on-chip peripherals L9803 98/126 note: the dir signal is internally synchronized with the pwm1 and pwm2 signals according to the selected driving mode. afte r writing the dir bit in bcsr register, the direction changes in correspondence with the first rising edge of pwm1. the same procedure is used in the case of pwm2. this allows the proper control of the direction changes. when the pwm signal is 0% or 100%, being no edges available, the dir bit can?t be latched and the direction does not change until a pwm edge occurs. pwm1 down brake mode 1 1 0 0 0 1 0 1 0 1 brake full bridge 1 1 0 1 0 1 1 0 0 1 forward full bridge 1 1 1 0 0 1 0 1 0 1 brake full bridge 1 1 1 1 0 1 0 1 1 0 back full bridge pwm1 symmetrical driving mode 1 1 0 0 1 0 0 1 1 0 back full bridge 1 1 0 1 1 0 1 0 0 1 forward full bridge 1 1 1 0 1 0 1 0 0 1 forward full bridge 1 1 1 1 1 0 0 1 1 0 back full bridge pwm1/pwm2 mode 1 1 0 1 1 pwm1 pwm1 pwm2 pwm2 pwm1 ->left pwm2->right tw o h a l f bridges 1 1 1 1 1 pwm1 pwm1 pwm2 pwm2 pwm1 ->left pwm2 ->right tw o h a l f bridges table 14. functional description table (continued) drive en pwm_en dir pwm1 in1 in2 ul dl ur dr operation configuration L9803 on-chip peripherals 99/126 figure 46. example - power bridge waveform, pwm up brake driving mode 5.8.6 register description the power section is controlled by the microcontroller through the following register: power bridge control status register (pbcsr) address: 0021h - read/write reset value: 00000000 bit 0 = en: power bridge enable. when reset the bridge is disabled and outl and outr are in high impedance condition. bit 1 = pwm_en : pwm driving enable. when reset the bridge is driven directly by in1 and in2 bit (direct mode). when set the driving is made by pwm1 and/or pwm2 bit according to the operation mode selected by in1 and in2 bit. bit 2 = in1 : left half bridge control bit if pwm_ en=0, driving mode selection bit if pwm_en=1. bit 3 = in2 : right half bridge control bit if pw m_en=0, driving mode selection bit if pwm_en=1. pwm1 dir ul dl ur dr outl outr back back back brake brake brake fwd fwd brake brake 7 0 pie ovt sc dir in2 in1 pwm_en en on-chip peripherals L9803 100/126 the following table summarizes the driving mode selection made by pwm_en, in1 and in2 bit bit 4 = dir : direction bit. this bit is meaningless when pwm_en=0. when pwm_en is set the dir bit controls the ?driving direction? of the bridge. in order to implement a precise control of the direction changes, dir value is latched by the rising edge of the pwm signal driving the bridge. when the signal does not have edges (i.e. pwm = 0% or 100%) the dir bit can not be latched and the driving directi on does not change even changing dir bit in bcsr. bit 5 = sc : short circuit flag (read only) bit 6 = ovt : overtemperature flag (read only) bit 7 = pie : power section interrupt enable. 5.9 eeprom (eep) 5.9.1 introduction the electrically erasable programmable read only memory is used to store data that need a non volatile back-up. the use of the eeprom re quires a basic protocol descri bed in this chapter. software or hardware reset and halt modes are managed immediately, stopping the action in progress. wait mode does not af fect the programming of the eeprom. the read operation of this memory is the same of a read-only-memory or ram. the erase and programming cycles are controlled by an eeprom control register. the user can program 1 to 4 bytes at the same programming cycle providing that the high part of the address is the same for the bytes to be written (only address bits a1 and a0 can change). the eeprom is mono-voltage. a charge pump genera tes the high voltage internally to enable the erase and programming cycles. th e erase and programming cycles are chained automatically. the global programming cycle duration is controlled by an internal circuit. pwm_en in1 in2 driving mode 0xxdirect 1 0 0 pwm1 up braking 1 0 1 pwm1 down braking 1 1 0 pwm1 symmetrical 111pwm1/pwm2 L9803 on-chip peripherals 101/126 figure 47. eeprom block diagram 5.9.2 functional description read operation (e2lat=0) the eeprom can be read as a normal rom/ra m location when the e2lat bit of the cr register is cleared. the address decoder selects the desired byte. the 8 sense amplifiers evaluate the stored byte which is put on the data bus. write operation (e2lat=1) the eeprom programming flowchart is shown in figure 49 . to access the write mode, the lat with e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 16 data latches according to its address. when e2pgm bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the eeprom cells . the effective high address (row) is determined by the last eeprom write sequence. to avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four least si gnificant bits of the address can change. buffer row decoder 4*8 bits data latches data multiplexer high voltage pump eeprom memory matrix 1 row = 4 * 8 bits address decoder address bus data bus e2ite e2lat e2pgm eepcr . . . . . . 32 32 8 8 4 4 12 interrupt request falling edge detector 8 bit read amplifiers on-chip peripherals L9803 102/126 at the end of the programming cycle, the e2pgm and e2lat bits are cleared simultaneously, and an interrupt is generated if the ie bit is set. the data eeprom interrupt request is cleared by hardware when the data eeprom interrupt vector is fetched. wait mode the eeprom can enter the wait mode by exec uting the wait instruction of the micro- controller. the eeprom will ef fectively enter this mode if there is no programming in progress, in such a case the eeprom will fi nish the cycle and then enter this low consumption mode. halt mode the eeprom enters the ha lt mode if the micro-controller di d execute the halt instruction. the eeprom will stop the function in progress, and will enter in this low consumption mode. figure 48. data eeprom programming cycle figure 49. eeprom programming flowchart e2lat erase cycle write cycle e2pgm t prog read operation not possible write of data latches read operation possible internal programming voltage eeprom interrupt e2lat=1 e2pgm=0 write bytes in eeprom e2lat=1 e2pgm=1 (start programming cycle) wait for end of programming (e2lat=0 or interrupt) write 1 to 4 bytes in the same row (with the same 12 most significant bits of the ad- e2lat=0 e2pgm=0 (read mode) L9803 on-chip peripherals 103/126 5.9.3 register description eeprom control register (eecr) address: 002ch - read/write reset value: 0000 0000 (00h) bit 7:3 = reserved, forced by hardware to 0. bit 2 = e2ite : interrupt enable. this bit is set and cleared by software. 0: interrupt disabled 1: interrupt enabled when the programming cycle is finished (e2pgm toggle from 1 to 0), an interrupt is generated only if e2ite is high. the interrupt is automatically cleared when the micro- controller enters the eepr om interrupt routine. bit 1 = e2lat : read/write mode. this bit is set by software. it is cleared by hardware at the end of the programming cycle. it can be cleared by software only if e2pgm=0. 0: read mode 1: write mode when e2lat=1, if the e2pgm bit is low and the micro-controller is in write mode, the 8 bit data bus is stored in one of the four groups of 8 bit data latches, selected by the address. this happens every ti me the device executes an eeprom write instruction. if e2pgm remains low, the content of the 8 bit data latches is not transferred into the matrix, because the high voltage charge-pump does not start. the 8 data latches are selected by the lower part of the address (a<1:0> bits). if 4 consecutive write instructions are executed, by sweeping from a<1:0>=0h to a<1:0>=3h, with the same higher part of the address, all the 4 groups of data latches will be written, and they will be ready to write a whole row of the eeprom matrix, as soon as e2pgm goes high and the charge- pump starts. if only one write instruction is executed before e2pgm goes high, only one group of data latches will be selected and only one byte of the matrix will be written. at th e end of the programming cycle, e2lat bit is automatically cleared, and the data latches are cleared. bit 0 = e2pgm : programming control. this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the e2ite bit is set. 0: programming finished or not started 1: programming cycle is in progress note: if the e2pgm bit is cleared during the programming cycle, the memory data is not guaranteed. note: care should be taken during the programming cycle. writing to the same memory location will over-program the memory (logical and between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the 7 0 00000 e2ite e2lat e2pgm on-chip peripherals L9803 104/126 falling edge of e2lat bit. it is not possible to read the latched data. special management of wrong eeprom access: if a read happens while e2lat=1, t hen the data bus will not be driven. if a write access happens while e2lat=0, then the data on the bus will not be latched. the data latches are cleared when the user sets e2lat bit. note: care should be taken in the write routine: the software has to read back the data and rewrite in case of failure. L9803 instruction set 105/126 6 instruction set 6.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two sub-modes called long and short: long addressing mode is more powerful bec ause it can use the full 64kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000 - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimize the use of long and short addressing modes. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 15. st7 addressing mode overview: mode syntax destination pointer address pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w] ,x) 0000..ffff 00..ff word + 2 instruction set L9803 106/126 inherent: all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10], #7,skip 00..ff 00..ff byte + 3 table 15. st7 addressing mode overview: (continued) mode syntax destination pointer address pointer size (hex.) length (bytes) inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles L9803 instruction set 107/126 immediate: immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. . direct (short, long): in direct instructions, the operands are referenced by their memory address, which follows the opcode. the direct addressing mode consists of two sub-modes: direct (short): the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff addressing space. direct (long): the address is a word, thus allowing 64kb addre ssing space, but requires 2 bytes after the opcode. immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations available long and short direct instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/substructions operations bcp bit compare short direct instru ctions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine instruction set L9803 108/126 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset which follows the opcode. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long): the offset is a word, thus allowing 64kb addressing space and requires 2 bytes after the opcode. no offset, long and short indexed instruction function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/substructions operations bcp bit compare no offset and short indexed instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2?s complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine L9803 instruction set 109/126 indirect (short, long): the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two sub- modes: indirect (short): the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long): the pointer address is a byte, the pointer size is a word, thus allowing 64kb addressing space, and requires 1 byte after the opcode. available long and short indirect instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/substructions operations bcp bit compare short indirect instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2?s complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine instruction set L9803 110/126 indirect indexed (short, long): this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short): the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long): the pointer address is a byte, the pointer size is a word, thus allowing 64kb addressing space, and requires 1 byte after the opcode. relative mode (direct, indirect): this addressing mode is used to modify the pc register value, by adding an 8 bit signed offset to it. long and short indirect indexed instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/substructions operations bcp bit compare short indirect indexed instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative L9803 instruction set 111/126 the relative addressing mode consists of two sub-modes: relative (direct): the offset is following the opcode. relative (indirect): the offset is defined in memory, which address follows the opcode. 6.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: using a pre-byte the instructions are described with one to four opcodes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different probate pockets are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf instruction set L9803 112/126 pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port a int pin = 1 (no port a interrupts) jril jump if port a int pin = 0 (port a interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? L9803 instruction set 113/126 jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m hinzc pop cc cc m push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z mnemo description function/example dst src h i n z c electrical characteristics L9803 114/126 7 electrical characteristics 7.1 absolute maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltage or electric fields. nevertheless, it is recommended that normal precautions be observed in order to avoid subjecting this high-impedance circuit to voltage above those quoted in the absolute maximum ratings. for proper operation, it is recommended that the input voltage v in , on the digital pins, be constrained within the range: (gnd - 0.3v) v in (v dd + 0.3v) to enhance reliability of operatio n, it is recommended to configure unused i/os as inputs and to connect them to an appropriate logic voltage level such as gnd or v dd . all the voltage in the following tables are referenced to gnd. table 16. absolute maximum ratings (voltage referenced to gnd) symbol ratings value unit vbr vbl = vb vb1 operating supply voltage t = 10s iso transients t = 400ms (1) 1. iso transient must not reset the device 0 to 18 0 to 24 0 to 40 v vbr=vbl dynamic destruction proof t<500us (single pulse) 0 to -2 v |agnd - gnd| max. variations (ground line) 50 mv t stg storage temperature range -55 to +150 c t j junction temperature 150 c esd esd susceptibility 2000 v v lv input voltage, low voltage pins gnd - 0.3 to v dd + 0.3 v v pwm pin voltage, pwmi, pwmo pins gnd - 18 to vb v v can pin voltage, can_h, can_l pins gnd - 18 to vb v i in input current (low voltage pins) -25.....+25 ma L9803 electrical characteristics 115/126 7.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja ) (1)* where: ?t a is the ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ?p d is the sum of p int and p i/o , ?p int is the product of i 1 and vb, plus the power dissipated by the power bridge, expressed in watts. this is the chip internal power ?p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o < electrical characteristics L9803 116/126 figure 50. hiquad-64: ja figure 51. hiquad-64: thermal impedance 1 2 3 4 5 6 7 dissipated power (w) 12 14 16 18 20 22 24 rth j-c (oc/w) die size 6x6 mm2 t amb. 22 oc natural convection 2s1p 1oz pcb multilayer optimised pcb 0 0 1 10 100 1,000 0 5 10 15 20 zth (oc/w) time (s) die size 6x6 mm2 power 6 w t amb. 22 oc natural convection 2s1p 1oz pcb multilayer optimised pcb
|
Price & Availability of L9803
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |